Dma Transactions; Figure 22. System Implementation Of The Two Dma Controllers - ST STM32F205 series Reference Manual

RM0033
See Figure 22

Figure 22. System implementation of the two DMA controllers

DMA controller 2
DMA controller 1
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2
streams are able to perform memory-to-memory transfers.
9.3.2

DMA transactions

A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-
programmable.
Each DMA transfer consists of three operations:
•
A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
• A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
for the implementation of the system of two DMA controllers.
DMA request
MAPPING
Bus matrix
(AHB
multilayer)
RM0033 Rev 8
DMA controller (DMA)
Flash
memory
112 KB SRAM
16 KB SRAM
AHB1 peripherals
AHB-APB
APB2
APB2
bridge2
peripherals
(dual AHB)
AHB-APB
APB1
APB1
bridge1
peripherals
(dual AHB)
AHB2 peripherals
External memory
controller (FSMC)
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