Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) - ST STM32F446 Series Reference Manual

Reset and clock control (RCC)
6.3.10

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.
31 30 29
OTGHS OTGHS
Res.
ULPIEN EN
rw rw
15 14 13
Res. Res. Res.
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
This bit is set and cleared by software.
0: USB OTG HS ULPI clock disabled
1: USB OTG HS ULPI clock enabled
Bit 29 OTGHSEN: USB OTG HS clock enable
This bit is set and cleared by software.
0: USB OTG HS clock disabled
1: USB OTG HS clock enabled
Bits 28:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
This bit is set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
This bit is set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 BKPSRAMEN: Backup SRAM interface clock enable
This bit is set and cleared by software.
0: Backup SRAM interface clock disabled
1: Backup SRAM interface clock enabled
Bits 17:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
This bit is set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
144/1328
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
CRC
Res. Res. Res.
EN
rw
24 23 22 21
DMA2 DMA1
Res. Res.
EN EN
rw rw
8 7 6 5
GPIOH GPIOG GPIOF
Res.
EN EN EN
rw rw rw
RM0390 Rev 4
20 19 18
BKP
Res. Res.
SRAMEN
rw
4 3 2
GPIOE GPIOD GPIOC
EN EN EN
rw rw rw
RM0390
17 16
Res. Res.
1 0
GPIOB GPIOA
EN EN
rw rw