Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) - ST STM32F412 Reference Manual

Reset and clock control (RCC) for STM32F412xx
6.3.10

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. CRCEN
rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and reset by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
138/1163
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0402 Rev 6
23 22 21
Res. DMA2EN DMA1EN
rw rw
7 6 5
GPIOH GPIOG GPIOF
EN EN EN
rw rw rw
20 19 18
Res. Res. Res. Res.
4 3 2
GPIOE GPIOD GPIOC GPIOB
EN EN EN EN
rw rw rw
RM0402
17 16
Res.
1 0
GPIOA
EN
rw rw