Rcc Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr) - ST STM32F410 Reference Manual

Reset and clock control (RCC)
5.3.8

RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
RNGEN Res. Res. Res.
rw
15 14 13 12
Res. Res. Res. CRCEN
rw
Bit 31 RNGEN: RNG clock enable
Set and cleared by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 30:23 Reserved, must be kept at reset value.
Bit 22 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and reset by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCEN: IO port C clock enable
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
116/771
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0401 Rev 3
23 22 21
Res. DMA2EN DMA1EN
rw rw
7 6 5
GPIOH
Res. Res.
EN
rw
RM0401
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
GPIOC GPIOB
Res. Res.
EN EN
rw rw
16
Res.
0
GPIOA
EN
rw