Table of Contents
Advertisement
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
Ø
A
to A
15
0
AS, RD
D
to D
7
0
(Read)
WR
D
to D
7
0
(Write)
WAIT
Figure 14-5. Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1 and 2)
14.3.2 Control Signal Timing
(1) Reset Input Timing
Ø
RES
T 2
T 1
t
t
WTS
WTH
t
RESS
Figure 14-6. Reset Input Timing
T W
t
t
WTS
WTH
t
RESS
263
T 3
t
RESW
Advertisement
Table of Contents
