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Security Engine (SEC)
26.5.5.3 Current Descriptor Pointer Register (CDPR)
CDPR1
CDPR2
CDPR3
CDPR4
Bits
63
62
61
Field
Type
Reset
Bits
47
46
45
Field
Type
Reset
Bits
31
30
29
Field
Type
Reset
Bits
15
14
13
Field
Type
Reset
The CDPR contains the address of the descriptor that the channel is currently processing. The bits
in the CDPR perform the functions described in Table 26-22.
Bits
Reset
—
63–36
EPTR
35–32
CUR_DES_PTR_ADRS
31–0
26-98
Current Descriptor Pointer Registers
60
59
58
57
44
43
42
41
—
28
27
26
25
CUR_DES_PTR_ADRS
12
11
10
9
CUR_DES_PTR_ADRS
Table 26-22. CDPR Bit Field Descriptions
0
Reserved. Write to zero for future compatibility.
0
Extended Pointer
Concatenated as the upper 4 bits of the pointer address when extended mode is
selected (EAE is high—see Table 26-18 for details).
0
Current Descriptor Pointer Address
Pointer to the system memory location of the current descriptor. This field reflects the
starting location in system memory of the descriptor currently loaded into the DB. This
value is updated whenever the channel requests a fetch of a descriptor from the controller.
The value from the Fetch FIFO is transferred to the current descriptor pointer register
immediately after the fetch is completed. This address is used as the destination for
writeback of the modified header, if header writeback notification is enabled.
MSC8144E Reference Manual, Rev. 3
56
55
54
53
52
—
R
0x0000
40
39
38
37
36
R
0x0000
24
23
22
21
20
R
0x0000
8
7
6
5
4
R
0x0000
Description
Offset 0xC1140
Offset 0xC1240
Offset 0xC1340
Offset 0xC1440
51
50
49
48
35
34
33
32
EPTR
19
18
17
16
3
2
1
0
Freescale Semiconductor
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