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Liquid Crystal Display Controller (LCDC)
22.3.24 LCDC Graphic Window DMA Control Register (LCD_GWDCR)
There is a 32 × 32 bit line buffer in the LCDC that stores graphic window data from system memory. The
graphic window DMA control register controls the DMA burst length and when to trigger a DMA burst in
terms of the number of data bytes left in the pixel buffer.
Address: 0xFC0A_C068 (LCD_GWDCR)
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
0 0 0 0 0 0 0 0 0 0
GWBT
W
Reset
1
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Figure 22-26. LCD Graphic Window DMA Control Register (LCD_GWDCR)
Field
31
Graphic window DMA burst type. Determines whether the burst length is fixed or dynamic in graphic window plane.
GWBT
0 Burst length is dynamic
1 Burst length is fixed
30–21
Reserved, must be cleared.
20–16
Graphic window DMA high mark. Establishes the high mark for DMA requests. For dynamic burst length, after the
GWHM
DMA request is made, data is loaded and the graphic window FIFO continues to be filled until the number of empty
longwords left in the graphic window FIFO is equal to the high mark minus 2. The minimum GWHM setting in dynamic
burst is 3. For fixed burst length, the burst length (in longwords) of each request is equal to the GWHM setting and
its value must be larger than GWTM.
15–5
Reserved, must be cleared.
4–0
Graphic window DMA trigger mark. Sets the low level mark in the graphic window FIFO to trigger a DMA request.
GWTM
The low level mark equals the number of longwords left in the pixel buffer.
22.3.25 Mapping RAM Registers (BGLUT and GWLUT)
There are two separate mapping RAMs in the LCD controller, the background lookup table (BGLUT) and
the graphic window lookup table (GWLUT). The BGLUT is for the background plane and the mapping
table is addressable from 0xFC0A_C800–0xFC0A_CBFC. The GWLUT is for the graphic window and
its mapping table is addressable from 0xFC0A_CC00–0xFC0A_CFFC.
These mapping RAMs are used for mapping 4-bit codes for grayscale to 16 gray shades, and for mapping
4-bit color and 8-bit color to 16 colors and 256 colors, respectively, out of a palette of 4096 (passive panels)
or 256K (active panels).
The mapping RAM contains 256 entries and each entry is accessed with longword transactions only and
the address must be longword aligned. Unimplemented bits are read as 0. All read and write data use the
least significant 12 or 18 bits.
Byte or word access to the RAM corrupts its contents.
22-26
GWHM
Table 22-27. LCD_GWDCR Field Descriptions
Description
NOTE
MCF5329 Reference Manual, Rev 3
Access: User read/write
8
7
0 0 0 0 0 0 0 0 0 0 0
6
5
4
3
2
1
0
GWTM
Freescale Semiconductor
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