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ARM Cortex M23 Generic User Manual

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Arm
Cortex
®
®
Revision: r2p0
Generic User Guide
Non-Confidential
Copyright © 2018, 2023 Arm Limited (or its affiliates).
All rights reserved.
-M23 Processor Device
Issue
DUI1095B_0200_en

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Summary of Contents for ARM Cortex M23

  • Page 1 Cortex -M23 Processor Device ® ® Revision: r2p0 Generic User Guide Non-Confidential Issue DUI1095B_0200_en Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved.
  • Page 2 No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
  • Page 3 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 4 Issue: Inclusive language commitment Arm values inclusive communities. Arm recognizes that we and our industry have used language that can be offensive. Arm strives to lead the industry and create change. This document includes language that can be offensive. We will replace this language in a future issue of this document.
  • Page 5 3.18 Data types..............................29 3.19 The Cortex Microcontroller Software Interface Standard..............30 3.20 Memory model............................31 3.21 Memory regions, types, and attributes....................32 3.22 Device memory............................32 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 5 of 162...
  • Page 6 4.2 CMSIS functions............................60 4.3 CMSE................................62 4.4 About the instruction descriptions......................62 4.5 Operands................................ 62 4.6 Restrictions when using PC or SP......................63 4.7 Shift Operations............................63 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 6 of 162...
  • Page 7 4.38 CMP and CMN............................86 4.39 MOV and MVN............................87 4.40 MOVT................................89 4.41 MULS................................89 4.42 REV, REV16, and REVSH.........................90 4.43 SDIV and UDIV............................91 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 7 of 162...
  • Page 8 5.9 Interrupt Target Non-secure Registers....................116 5.10 Interrupt Priority Registers........................116 5.11 Level-sensitive and pulse interrupts....................117 5.12 Hardware and software control of interrupts................... 118 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 8 of 162...
  • Page 9 5.44 MPU Control Register..........................143 5.45 MPU Region Number Register......................145 5.46 MPU Region Base Address Register....................145 5.47 MPU Region Limit Address Register....................146 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 9 of 162...
  • Page 10 6.4 Flop Parity..............................157 6.5 STL support components.........................158 6.6 FUSAEN I/O for debug and trace logic protection................159 6.7 STL registers..............................159 A. Revisions..............................162 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 10 of 162...
  • Page 11 1. Introduction 1.1 Implementation obligations This book is designed to help you implement an Arm product. The extent to which the deliverables may be modified or disclosed is governed by the contract between Arm and Licensee. There may be validation requirements, which if applicable will be detailed in the contract between Arm and Licensee and which if present must be complied with prior to the distribution of any silicon devices incorporating the technology described in this document.
  • Page 12 Glossary is a list of terms used in Arm documentation, together with definitions for ® those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Arm Glossary for more information: developer.arm.com/glossary.
  • Page 13 • HIGH for active-HIGH signals. • LOW for active-LOW signals. Lowercase n At the start or end of a signal name, n denotes an active-LOW signal. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 13 of 162...
  • Page 14 IEEE Standardfor Binary Floating-Point Arithmetic. ANSI/IEEE Std 754-2008 Arm tests its PDFs only in Adobe Acrobat and Acrobat Reader. Arm cannot guarantee the quality of its documents when used with any other PDF reader. Adobe PDF reader products can be downloaded at http:/ /www.adobe.com.
  • Page 15 15. 2.1 About the Cortex-M23 processor and core peripherals The Cortex-M23 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: • A simple architecture that is easy to learn and program.
  • Page 16 The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs), significantly reducing the interrupt latency. This is achieved through the hardware Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 17 The breakpoint unit provides up to four hardware breakpoint comparators that debuggers can use. The data watchpoint unit provides up to four data watchpoint comparators that debuggers can use. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 18 • In an implementation that does not support the Security Extension, either: ◦ No SysTicks are implemented. ◦ One SysTick is implemented. Security Attribution Unit The optional SAU determines the security of an address. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 18 of 162...
  • Page 19 • Memory Protection Unit for Armv8-M based platforms. • Arm ® v8-M Architecture Reference Manual. • TrustZone ™ technology for Armv8-M Architecture. • Introduction to the Armv8-M Architecture. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 19 of 162...
  • Page 20 • Cannot access the system timer, NVIC, or system control block. • Might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 20 of 162...
  • Page 21 Privilege level for software execution Stack used Thread Applications Privileged or unprivileged Main stack or process stack Handler Exception handlers Always privileged Main stack Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 21 of 162...
  • Page 22 0x00000000 EPSR 3.12 Execution Program Status Register on page 26. Unknown  3.16 CONTROL register on page 28. PSR includes APSR, IPSR, and EPSR. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 22 of 162...
  • Page 23 In a processor with the Security Extension implemented, the register is banked between Secure and Non-secure state. Bit[24] is the T-bit and is loaded from bit[0] of the reset vector. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 23 of 162...
  • Page 24 APSR, EPSR, and IPSR. IEPSR EPSR and IPSR. IAPSR APSR and IPSR. EAPSR APSR and EPSR. The processor ignores writes to the IPSR bits. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 24 of 162...
  • Page 25 The last bit of the Exception number bit field depends on the number of interrupts implemented.0-47 interrupts = [5:0].48-111 interrupts = [6:0].112-239 interrupts = [7:0]. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 25 of 162...
  • Page 26 Attempts to write the EPSR using the instruction are ignored. The following can clear the T bit to 0: • Instructions and, POP{PC} Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 26 of 162...
  • Page 27 Table 3-2: Core register set summary on page 22 for its attributes. The bit assignments are: Reserved Table 3-8: PRIMASK register bit assignments Bits Name Function [31:1] Reserved. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 27 of 162...
  • Page 28 0 = MSP is the current Stack Pointer. 1 = PSP is the current Stack Pointer. In Handler mode this bit is ignored, the processor always uses the MSP. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 28 of 162...
  • Page 29 The SPSEL bit can be written at any time, but in Handler mode MSP is always used, regardless of the value of SPSEL. In an OS environment, Arm recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack.
  • Page 30 60. • 5.3 Accessing the Cortex-M23 NVIC registers using CMSIS on page 111. • 5.14 NVIC programming hints on page 119. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 30 of 162...
  • Page 31 The processor reserves regions of the Private Peripheral Bus (PPB) address range for core peripheral registers, see 2.1 About the Cortex-M23 processor and core peripherals on page 15. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 31 of 162...
  • Page 32 Gathering or non-Gathering. Multiple accesses to a device can be merged into a single transaction except for operations with memory ordering semantics, for example, memory barrier instructions, load acquire/store release. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 32 of 162...
  • Page 33 NSC is a special type of Secure location. This type of memory is the only type which an Armv8-M processor permits to hold an instruction that enables software to transition from Non-secure to Secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 33 of 162...
  • Page 34 TPIU configuration registers or none. 0xE0050000- Private XN Reserved. 0xE00EFFFF Peripheral Bus 0xE00F0000- Device Device XN This region includes the Cortex-M23 MCU ROM when implemented. 0xE00FFFFF Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 34 of 162...
  • Page 35 3.21 Memory regions, types, and attributes on page 31 for more information. WT = Write through, no write allocate. WBWA = Write back, write allocate. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 35 of 162...
  • Page 36 If the system contains a memory map switching mechanism, use a instruction after switching the memory map. This ensures subsequent instruction execution uses the updated memory map. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 36 of 162...
  • Page 37 A Store-Exclusive instruction Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 37 of 162...
  • Page 38 3. If the returned status bit from step on page 38 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 38 of 162...
  • Page 39 In any other case, exclusive information is not sent on the AHB bus, HEXCL is 0, and only the local monitor is used. If HEXCL is sent externally and there is no exclusive monitor for the corresponding memory region, then fails. STREX Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 39 of 162...
  • Page 40 Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 40 of 162...
  • Page 41 Priority -1. A HardFault is an exception that occurs because of an error during normal or exception processing. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 41 of 162...
  • Page 42 This exception is not banked between security states. Secure code can assign each interrupt to Secure or Non-secure state. By default all interrupts are assigned to Secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 43 The IPSR returns the Exception number, see 3.11 Interrupt Program Status Register on page 25. 5.10 Interrupt Priority Registers on page 116. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 43 of 162...
  • Page 44 Secure and Non-secure state when Security Extensions are implemented. The least-significant bit of each vector must be 1, indicating that the exception handler is written in Thumb code. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 44 of 162...
  • Page 45 The silicon vendor must configure the required alignment, which depends on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts. For Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 46 When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 47 • The new exception is of higher priority than the exception being handled, in which case the new exception preempts the exception being handled. When one exception preempts another, the exceptions are nested. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 47 of 162...
  • Page 48 Secure code. The extented stack frame is also used in case of late arrival of exceptions and the final exception is Secure. In case of tail-chaining, some stacking might be required to extend the stack if it was not already full. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 48 of 162...
  • Page 49 This is the late arrival case. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 49 of 162...
  • Page 50 1 = Thread mode. SPSEL Indicates which Stack Pointer the exception frame resides on. 0 = Main Stack Pointer. 1 = Process Stack Pointer. Reserved. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 50 of 162...
  • Page 51 40. All the faults that occur in the NMI or HardFault handler might result in the HardFault exception being taken or cause lockup. See the Arm®v8-M Architecture Reference Manual for M profile. The faults can be divided into three categories: Copyright ©...
  • Page 52 Only Reset and NMI can preempt the fixed priority HardFault handler. A HardFault at priority -3 (when BFHFNMINS is set to 1) can preempt NMI or a HardFault at priority -1. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 52 of 162...
  • Page 53 For this reason, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back in to sleep mode. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 54 Sleep-on-exit is banked between security states. If returning to Secure state, use the Secure instance. If returning to Non-secure state, use the Non-secure instance. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 54 of 162...
  • Page 55 When the WIC is enabled and the processor enters deep sleep mode, the power management unit in the system can power down most of the Cortex-M23 processor. This has the side effect of stopping the SysTick timer. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 55 of 162...
  • Page 56 __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt void __SEV(void) // Send Event Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 56 of 162...
  • Page 57 4.33 ADC, ADD, RSB, SBC, and SUB on page {Rd,} Rn, <Rm| #imm> PC-relative Address to Register 4.18 ADR on page 69 Rd, label Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 57 of 162...
  • Page 58 4.17 Memory access instructions on page LDRH Rt, [Rn, <Rm| #imm>] Load Register Signed Byte 4.17 Memory access instructions on page LDRSB Rt, [Rn, <Rm| #imm>] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 58 of 162...
  • Page 59 4.17 Memory access instructions on page Rt, [Rn, <Rm| #imm>] Store Register Byte 4.17 Memory access instructions on page STRB Rt, [Rn, <Rm| #imm>] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 59 of 162...
  • Page 60 __ISB (void) void __DSB (void) void __DMB (void) uint32_t __LDA (volatile uint32_t * ptr ) LDAB uint8_t __LDAB (volatile uint8_t * ptr ) Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 60 of 162...
  • Page 61 Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) The CMSIS also provides several functions for accessing the Non-secure special registers using instructions: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 61 of 162...
  • Page 62 • 4.5 Operands An instruction operand can be an Arm register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved.
  • Page 63 When the instruction is the carry flag is updated to the last bit shifted out, bit[ -1], of the ASRS register Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 63 of 162...
  • Page 64 • If is 33 or more and the carry flag is updated, it is updated to 0. Figure 4-2: LSR #3 Carry Flag Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 64 of 162...
  • Page 65 flag is updated, it is updated to bit[31] of with shift length, , greater than 32 is the same as with shift length • -32. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 65 of 162...
  • Page 66 See the instruction descriptions for the flags they affect. You can execute a conditional branch instruction, based on the condition flags set in another instruction, either: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 66 of 162...
  • Page 67 The Compare operations are identical to subtracting, for , or adding, for , except that the result is discarded. See the instruction descriptions for more information. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 67 of 162...
  • Page 68 4.28 LDREX and STREX on page 75. LDREX{type} Load Register using immediate offset 4.20 LDR and STR, immediate offset on page 71. LDR{type} Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 68 of 162...
  • Page 69 66. Operation generates an address by adding an immediate value to the PC, and writes the result to the destination register. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 69 of 162...
  • Page 70 STREXH LDREX valid and does not fail. enables compatibility with other Arm Cortex processors that have to force the failure of CLREX the store exclusive if the exception occurs between a load-exclusive instruction and the matching store-exclusive instruction in a synchronization operation. In Cortex-M processors, the local exclusive access monitor clears automatically on an exception boundary, so exception handlers using CLREX are optional.
  • Page 71 R0-R7 as the base register. ◦ 0 and 62 and an integer multiple of two for LDRH STRH ◦ 0 and 31 for LDRB STRB Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 71 of 162...
  • Page 72 The memory address to load from or store to is the sum of the values in the registers specified by Restrictions In these instructions: • , and must only specify R0-R7. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 72 of 162...
  • Page 73 ; Load R0 with a word of data from an address ; labelled as LookUpTable. R3, [PC, #100] ; Load R3 with memory word at (PC + 100). Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 73 of 162...
  • Page 74 + 4 * is written back to the register specified by 4.26 LDM and STM restrictions In these instructions: are limited to R0-R7. • reglist Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 74 of 162...
  • Page 75 Operation , and load a word, byte, and halfword respectively from a memory address. LDREX LDREXB LDREXH Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 75 of 162...
  • Page 76 • For must be different from both STREX • The value of must be a multiple of four in the range 0-1020. offset Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 76 of 162...
  • Page 77 Loads and stores appearing after a store-release are unaffected. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 77 of 162...
  • Page 78 Is the destination register into which the status result of the store exclusive is written. Is the register to load or store. Is the register on which the memory address is based. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 78 of 162...
  • Page 79 ; Did this succeed? BNE try ; No – try again ; Yes – we have the lock. unlock MOV r1, #0 STL r1, [r0] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 79 of 162...
  • Page 80 PUSH {R2,LR} ; Push R2 and the link-register onto the stack {R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 80 of 162...
  • Page 81 4.44 SXT and UXT on page 92. Unsigned Extend Halfword 4.44 SXT and UXT on page 92. UXTH Test 4.45 TST on page 93. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 81 of 162...
  • Page 82 flags. instruction subtracts the value in or the immediate specified by imm from Rn. It places the result in the register specified by Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 82 of 162...
  • Page 83 R4, R5, and R6. The example stores the result in R4, R5, and R6. Arithmetic negation on page 84 shows the instruction used to perform a 1's complement RSBS of a single register. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 83 of 162...
  • Page 84 The condition code flags are updated on the result of the operation, see 4.15 The condition flags on page 67. Restrictions In these instructions, , and must only specify R0-R7. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 84 of 162...
  • Page 85 Is the shift length. The range of shift length depends on the instruction: shift length from 1 to 32 shift length from 0 to 31 shift length from 1 to 32. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 85 of 162...
  • Page 86 CMN Rn, Rm CMP Rn, #imm CMP Rn, Rm where: Is the register holding the first operand. Is the register to compare with. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 86 of 162...
  • Page 87 R0, R2 4.39 MOV and MVN Move and Move NOT. Syntax MOV{S} Rd, Rm MOVS Rd, #imm8 MOV{W} Rd, #imm16 MVNS Rd, Rm where: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 87 of 162...
  • Page 88 R8, SP ; Write value of stack pointer to R8 MVNS R2, R0 ; Write inverse of R0 to the R2 and update flags Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 88 of 162...
  • Page 89 Multiply using 32‑bit operands, and producing a 32-bit result. Syntax MULS Rd, Rn, Rm where: Is the destination register. Rn, Rm Are registers holding the values to be multiplied. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 89 of 162...
  • Page 90 REV16 Rd, Rn REVSH Rd, Rn Where: Is the destination register. Is the source register. Operation Use these instructions to change endianness of data: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 90 of 162...
  • Page 91 SDIV instruction performs an unsigned integer division of the value in by the value in UDIV Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 91 of 162...
  • Page 92 32 bits. • SXTH extracts bits[15:0] and zero extends to 32 bits. • UXTH Restrictions In these instructions, must only specify R0-R7. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 92 of 162...
  • Page 93 • Updates the N and Z flags according to the result. • Does not affect the C or V flags. Examples R0, R1 ; Perform bitwise AND of R0 value and R1 value, Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 93 of 162...
  • Page 94 66. label Is a PC‑relative expression. See 4.13 PC‑relative expressions on page 66. Is a register providing the address to branch to. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 94 of 162...
  • Page 95 ; in R0 labelD ; Conditionally branch to labelD if last flag setting ; instruction set the Z flag, else do not branch. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 95 of 162...
  • Page 96 For information about how to build a Secure image that uses a previously generated import library, see the Arm Compiler Software Development Guide. ® Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 96 of 162...
  • Page 97 These instructions do not change the flags. Examples R5, target ; Forward branch if R5 is zero CBNZ R0, target ; Forward branch if R0 is not zero Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 97 of 162...
  • Page 98 Debug state. Debug tools can use this to BKPT investigate system state when the instruction at a particular address is reached. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 98 of 162...
  • Page 99 0x80, and does not mask Secure interrupts with a lower priority value. CPSIE i ; Enable interrupts (clear PRIMASK.PM) Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 99 of 162...
  • Page 100 Restrictions There are no restrictions. Condition flags This instruction does not change the flags. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 100 of 162...
  • Page 101 Is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL. can also be MSP_NS, PSP_NS, MSPLIM, PSPLIM, spec_reg CONTROL_NS, PRIMASK_NS in Secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 101 of 162...
  • Page 102 4.57 MRS on page 101. Restrictions In this instruction, must not be SP and must not be PC. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 102 of 162...
  • Page 103 Restrictions There are no restrictions. Condition flags This instruction does not change the flags. Examples ; No operation 4.60 SEV Send Event. Syntax Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 103 of 162...
  • Page 104 For information about how to build a Secure image that uses a previously generated import library, see the Arm ® Compiler Software Development Guide. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 104 of 162...
  • Page 105 Syntax {op} Rd, Rn, label Where: Is one of: Test Target (TT) queries the security state and access permissions of a memory location. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 105 of 162...
  • Page 106 Set to 0 if the IREGION content is invalid.This bit is always 0 if the IDAU cannot provide a region number, the address is exempt from security attribution, or if the requesting TT instruction is executed from the Non-secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 107 When writing software assume that might behave as Restrictions There are no restrictions. Condition flags This instruction does not change the flags. Examples ; Wait for event Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 107 of 162...
  • Page 108 Restrictions There are no restrictions. Condition flags This instruction does not change the flags. Examples WFI ; Wait for interrupt Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 108 of 162...
  • Page 109 -M23 Processor Device Generic User Guide Issue: Cortex-M23 Peripherals 5. Cortex-M23 Peripherals The following sections are the reference material for the Arm Cortex-M23 core peripherals descriptions in a User Guide: It contains the following sections: 5.1 About the Cortex-M23 peripherals on page 109.
  • Page 110 5.6 Interrupt Set-pending Registers on page 113. 0xE000E200-0xE000E23C 0x00000000 0xE002E200-0xE002E23C NVIC_ISPR0_NS - 0x00000000 NVIC_ISPR7_NS Depending on NVIC_ITNS, bits can be RAZ/WI from Non- secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 110 of 162...
  • Page 111 1. IRQn) Sets the priority of an interrupt or exception with configurable priority level to 1. void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 111 of 162...
  • Page 112 The input parameter IRQn is the IRQ number, see Table 3-13: Properties of the different exception types on page 43 for more information. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 112 of 162...
  • Page 113 110 for the register attributes. Register bits can be RAZ/WI depending on the value of ITNS. The bit assignments are: SETPEND[32n+31:32n] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 113 of 162...
  • Page 114 110 for the register attributes. Register bits can be RAZ/WI depending on the value of ITNS. The bit assignments are: CLRPEND[32n+31:32n] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 114 of 162...
  • Page 115 Table 5-8: NVIC_IABRn bit assignments Bits Name Function [31:0] ACTIVE Active state bits. 0 = The interrupt is not active. 1 = The interrupt is active. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 115 of 162...
  • Page 116 Each register holds four priority fields as shown: 24 23 16 15 NVIC_IPR59 PRI_239 PRI_238 PRI_237 PRI_236 NVIC_IPRn PRI_(4n+3) PRI_(4n+2) PRI_(4n+1) PRI_(4n) NVIC_IPR0 PRI_3 PRI_2 PRI_1 PRI_0 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 116 of 162...
  • Page 117 A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 118 For a pulse interrupt, state of the interrupt changes to: ◦ Inactive, if the state was pending. ◦ Active, if the state was active and pending. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 118 of 162...
  • Page 119 5.19 Application Interrupt and Reset Control Register on page 125. 0xE000ED0C 0xFA050000   AIRCR_NS 0xE002ED0C 0xFA050000 0xE000ED10 SCR_S 0x00000000 5.20 System Control Register on page 126. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 119 of 162...
  • Page 120 0x41 = Arm. [23:20] VARIANT Major revision number n in the rnpm revision status: 0x2 = Revision 2. See the register description for more information. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 120 of 162...
  • Page 121 The bit assignments are: 30 29 27 26 23 22 21 20 12 11 VECTPENDING RES0 VECTACTIVE ISRPENDING ISRPREEMPT STTNS PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET PENDNMICLR PENDNMISET Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 121 of 162...
  • Page 122 1 = PendSV exception is pending. [27] PENDSVCLR This bit is banked between security states. PendSV clearing-pending bit. 0 = No effect. 1 = Clear pending status. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 122 of 162...
  • Page 123 0 = Will not service. 1 = Will service a pending exception. When the debug extensions are not implemented, this bit is RAZ/WI. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 123 of 162...
  • Page 124 • Exceptions that target Non-secure state use VTOR_NS to determine the base address of the Non-secure vector table. The bit assignments are: TBLOFF Reserved Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 124 of 162...
  • Page 125 0-47 interrupts = [31:7]. • 48-111 interrupts = [31:8]. 112-239 interrupts = [31:9]. • 0-47 interrupts = [31:7].48-111 interrupts = [31:8].112-239 interrupts = [31:9]. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 125 of 162...
  • Page 126 This bit is WO and can only be written when the processor is in Halt state. This bit is not banked between security states. Reserved. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 126 of 162...
  • Page 127 Controls whether the processor uses sleep or deep sleep as its low-power mode: 0 = Sleep. 1 = Deep sleep. This bit is not banked between security states. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 127 of 162...
  • Page 128 Bits Name Function [31:19] Reserved. [18] RAZ/WI. [17] RAZ/WI. [16] RAZ/WI. [15:11] Reserved. [10] STKOFHFNMIGN 0 = RAZ/WI. RES1. BFHFNMIGN 0 = RAZ/WI. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 128 of 162...
  • Page 129 The SVCall and PendSV handlers are always banked between security states. Priorities values depend on the value of PRIS, as described in Table 3-14: Extended priority on page Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 129 of 162...
  • Page 130 If the Security Extension, one SysTick is implemented, and STTNIS is 1, then it is RAZ/WI from Non-secure state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 130 of 162...
  • Page 131 0 = PendSV exception is not active for the selected security state. 1 = PendSV exception is active for the selected security state. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 131 of 162...
  • Page 132 The ACTLR contains several fields that allow software to control the processor features and functionality. The bit assignments are: Reserved EXTEXCLALL Reserved Table 5-22: ACTLR bit assignments Bits Name Function [31:30] - RAZ/WI. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 132 of 162...
  • Page 133 0x00000000 0xE000E014 SYST_RVR Unknown 5.30 SysTick Reload Value Register on page 135. 0xE000E018 SYST_CVR Unknown 5.32 SysTick Current Value Register on page 135. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 133 of 162...
  • Page 134 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero asserts the SysTick exception request. SysTick calibration value. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 134 of 162...
  • Page 135 The SYST_CVR contains the current value of the SysTick counter. See the register summary in Table 5-23: System timer registers summary on page 133 for its attributes. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 135 of 162...
  • Page 136 SysTick as a software real-time clock. [29:24] - Reserved. [23:0] TENMS Reads as zero. Indicates calibration value is not known. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 136 of 162...
  • Page 137 When a memory access is performed, the SAU is required. Any address that matches multiple SAU regions is marked as Secure regardless of the attributes that are specified by the regions that matched the address. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 137 of 162...
  • Page 138 This is the reset value when the Security Extension is implemented. If the Security Extension is not implemented, the reset value is 00000002. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 138 of 162...
  • Page 139 The SAU_TYPE bit assignments are: Reserved SREGION Table 5-30: SAU_TYPE bit assignments Bits Name Function [31:8] Reserved. [7:0] SREGION SAU regions. The number of implemented SAU regions. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 139 of 162...
  • Page 140 Base address. Holds bits [31:5] of the base address for the selected SAU region. Bits [4:0] of the base address are defined as 0x00. [4:0] Reserved. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 140 of 162...
  • Page 141 The MPU is divided into regions and defines the location, size, access permissions, and memory attributes of each region. It supports: • Independent attribute settings for each region. • Export of memory attributes to the system. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 141 of 162...
  • Page 142 0xE000ED98 MPU_RNR UNKNOWN 5.45 MPU Region Number Register on page 145. 0xE000ED9C MPU_RBAR UNKNOWN 5.46 MPU Region Base Address Register on page 145. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 142 of 162...
  • Page 143 • Whether the default memory map is enabled as a background region for privileged accesses. • Whether the MPU is enabled for HardFaults, and NMIs. The MPU_CTRL bit assignments are: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 143 of 162...
  • Page 144 When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 145 Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. The MPU_RBAR bit assignments are: 3 2 1 BASE AP[2:1] Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 145 of 162...
  • Page 146 The MPU_RLAR provides indirect read and write access to the limit address of the currently selected MPU region for the selected Security state. The MPU_RLAR bit assignments are: Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 146 of 162...
  • Page 147 Attr<n>, bits [8n+7:8n], for n= 0 to 3. Memory attribute encoding for MPU regions with an AttrIndex of n. The MPU_MAIR1 bit assignments are: Attr7 Attr6 Attr5 Attr4 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 147 of 162...
  • Page 148 Device attributes. Specifies the memory attributes for Device.The possible values of this field are: 0b00 Device-nGnRnE. 0b01 Device-nGnRE. 0b10 Device-nGRE. 0b11 Device-GRE. When MAIR_ATTR[7:4] is not 0000 Outer Inner Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 148 of 162...
  • Page 149 Normal memory, Inner write-back non-transient. R and W specify the outer read and write allocation policy: 0 = do not allocate, 1 = allocate. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 149 of 162...
  • Page 150 MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then you do not require an Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 151 In most microcontroller implementations, the cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential...
  • Page 152 68. The I/O port does not support code execution and does not support all forms of exclusive Load and Store. If implemented, the I/O port can be protected by the MPU and SAU. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 152 of 162...
  • Page 153 • AHB Manager I/O port • SBIST APB • The options are: Interface protection is excluded. Interface protection is included. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 153 of 162...
  • Page 154 Include parity on flip- flops No parity on flip-flops Note: If FLOPPARITY is set to 1, then RAR must also be set to 1. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 154 of 162...
  • Page 155 Must be set to 0 for correct operation of the Execution Testbench. • The Software Test Library (STL) can set to 1 for additional coverage. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 155 of 162...
  • Page 156 HWDATA checked in data phase for write transfer HRDATA checked in data phase for read transfer and HREADY HRESP and HEXOKAY checked in data phase Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 156 of 162...
  • Page 157 The error signals from the logic associated System power domain and the top level power domain are combined separately and output on the external signal DFE. Flop parity is configured at implementation using the Verilog parameter FLOPPARITY. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 157 of 162...
  • Page 158 159 describes the registers associated with these observation points. The SBIST controller unit and the trickboxes are included in the MCU layer. Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 158 of 162...
  • Page 159 Function [31:19] RES0 [18] VALID Priority tree output is valid [17] TARGET Exception Security target • 0 = Secure 1 = Non-Secure • Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 159 of 162...
  • Page 160 [4:3] RES0 INSTR Select Instruction MPU DATA Select Data MPU RES0 Table 6-5: STLAMPUOR and STLBMPUOR observation registers Bits Field Function [31:17] RES0 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 160 of 162...
  • Page 161 MPU_S and MPU_NS • HITREGION[7:4] is RAZ This field is RAZ for STLBMPUOR [8:6] RES0 [5:0] ATTR Memory attributes: ATTR[5]: Shareability ATTR[4:0] : Attributes Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 161 of 162...
  • Page 162 150 Added functional safety features chapter. 6. Functional safety features on page 153 r2p0 Copyright © 2018, 2023 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 162 of 162...