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ST STM32F7 Series Application Notes

ST STM32F7 Series Application Notes

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Getting started with STM32F7 Series MCU hardware development
Introduction
This application note is intended for system designers who require an hardware
implementation overview of the development board, with a focus on the features:
• Power supply,
• Package selection,
• Clock management,
• Reset control,
• Boot mode settings,
• Debug management.
This document describes the minimum hardware resources required to develop an
application based on the STM32F7 Series devices.
Reference documents
The following documents are available on www.st.com:
•
Oscillator design guide for STM8S, STM8A and STM32 microcontrollers
application note (AN2867),
• STM32 microcontroller system memory boot mode application note (AN2606).
February 2017
DocID027559 Rev 5
AN4661
Application note
1/54
www.st.com
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  • Page 1 AN4661 Application note Getting started with STM32F7 Series MCU hardware development Introduction This application note is intended for system designers who require an hardware implementation overview of the development board, with a focus on the features: • Power supply, • Package selection, •...

  • Page 2: Table Of Contents

    Contents AN4661 Contents Power supplies ..........7 Introduction .
  • Page 3 STM32F7 Series devices ........
  • Page 4 Contents AN4661 8.4.3 Quadrature serial parallel interface (Quad-SPI) ....46 8.4.4 Embedded trace macrocell (ETM) ......47 Package layout recommendation .
  • Page 5 Boot modes............. 27 Table 3. STM32F7 Series bootloader communication peripherals ......28 Table 4.
  • Page 6 Six layer PCB stack-up example ..........43 Figure 27. Example of bypass cap placed underneath the STM32F7 Series ....44 Figure 28.

  • Page 7: Power Supplies

    AN4661 Power supplies Power supplies Introduction The device requires a 1.8 to 3.6 V operating voltage supply (V ), which can be reduced down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear voltage regulator is used to supply the internal 1.2 V digital power. The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V voltage when the main V...

  • Page 8: Figure 1. Vddusb Connected To Vdd Power Supply

    Power supplies AN4661 Figure 1. V connected to V power supply DDUSB Figure 2. V connected to external power supply. DDUSB In the STM32F7x3xx devices, the USB PHY HS sub-system uses an additional power supply pin: • The V pin is the output of the PHY HS regulator (1.2 V). An external DD12OTGHS capacitor of 2.2 µF must be connected on the V pin.

  • Page 9: Independent Sdmmc2 Supply For Stm32F767Xx/Stm32F777Xx And Stm32F72Xxx/Stm32F73Xxx Devices

    AN4661 Power supplies 1.1.3 Independent SDMMC2 supply for STM32F767xx/STM32F777xx and STM32F72xxx/STM32F73xxx devices The V is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7, DDSDMMC PG9..12). It can be connected either to V or an external independent power supply. For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V .

  • Page 10: Independent Dsi Supply For Stm32F769Xx/Stm32F779Xx Devices

    Power supplies AN4661 1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins: • The V is an independent DSI power supply dedicated for DSI Regulator and MIPI DDDSI DPHY.

  • Page 11: Power Supply Scheme

    AN4661 Power supplies Power supply scheme • = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V pins. The V pins must be connected to with external decoupling capacitors: one single tantalum or ceramic capacitor (min.

  • Page 12: Figure 4. Power Supply Overview (Stm32F74Xxx/Stm32F75Xxx)

    Power supplies AN4661 Figure 4. Power supply overview (STM32F74xxx/STM32F75xxx) 1. Optional. If a separate, external reference voltage is connected on V , the two capacitors (100 nF and 1 REF+ μF) must be connected. 2. V is either connected to V or to V (depending on package).

  • Page 13: Figure 5. Stm32F769Xx/Stm32F779Xx Power Supply Scheme

    AN4661 Power supplies Figure 5. STM32F769xx/STM32F779xx power supply scheme 1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 2. The 4.7 µF ceramic capacitor must be connected to one of the V pin.
  • Page 14 Power supplies AN4661 Figure 6. STM32F767xx/STM32F777xx power supply scheme 1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 2. The 4.7 µF ceramic capacitor must be connected to one of the V pin.
  • Page 15 AN4661 Power supplies Figure 7. STM32F7x2xx power supply scheme 1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 2. The 4.7 µF ceramic capacitor must be connected to one of the V pin.
  • Page 16 Power supplies AN4661 Figure 8. STM32F7x3xx power supply scheme 1. The V allows supplying the PHY FS in PA11/PA12 and the PHY HS on PB14/PB15. DDUSB 16/54 DocID027559 Rev 5...

  • Page 17: Reset & Power Supply Supervisor

    AN4661 Power supplies 2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 µF ceramic capacitor must be connected to one of the V pin. 4.

  • Page 18: System Reset

    Power supplies AN4661 A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to indicate if V is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when V drops below the PVD threshold and/or when V...

  • Page 19: Internal Reset On

    AN4661 Power supplies Figure 11. Reset circuit 1.3.4 Internal reset ON On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. For more details about the internal reset ON, refer to the datasheets (DS10915, DS10916). 1.3.5 Internal reset OFF This feature is available only on the packages featuring the PDR_ON pin.

  • Page 20: Figure 13. Nrst Circuitry Timing Example

    Power supplies AN4661 The supply ranges which never go below 1.8V minimum should be better managed by the internal circuitry (no additional component needed, thanks to the fully embedded reset controller). When the internal reset is OFF, the following integrated features are no more supported: •...

  • Page 21: Regulator Off Mode

    AN4661 Power supplies 1.3.6 Regulator OFF mode Refer to Voltage regulator section in the datasheet for details. • When BYPASS_REG = V , the core power supply should be provided through V CAP1 and V pins connected together. CAP2 – The two V ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

  • Page 22: Regulator On/Off And Internal Reset On/Off Availability

    Power supplies AN4661 The following conditions must be respected: • should always be higher than V to avoid a current injection between power domains. • If the time for V to reach V12 minimum value is smaller than the time for V reach 1.7 V, then PA0 should be kept low to cover both conditions: until V reaches V12 minimum value and until V...

  • Page 23: Alternate Function Mapping To Pins

    Alternate function mapping to pins Alternate function mapping to pins In order to easily explore the peripheral alternate functions mapping to the pins it is recommended to use the STM32CubeMX tool available on www.st.com. Figure 15. STM32CubeMX example screen-shot DocID027559 Rev 5...

  • Page 24: Clocks

    Clocks AN4661 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator clock. • HSE oscillator clock. • Main PLL (PLL) clock. The devices have the two following secondary clock sources: • 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.

  • Page 25: External Crystal/Ceramic Resonator (Hse Crystal)

    AN4661 Clocks 3.1.2 External crystal/ceramic resonator (HSE crystal) The external oscillator frequency ranges from 4 to 26 MHz. The external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 17.

  • Page 26: External Clock (Lse Bypass)

    Clocks AN4661 The LSE oscillator includes new modes and has a configurable drive using the LSEDRV [1:0] in RCC_BDCR register: • 00: Low drive. • 10: Medium low drive. • 01: Medium high drive. • 11: High drive. The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not.

  • Page 27: Boot Configuration

    Boot configuration Boot configuration Boot mode selection In the STM32F7 Series, two different boot spaces can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 or BOOT_ADD1 option bytes as shown in the Table Table 2.

  • Page 28: Boot Pin Connection

    1. Resistor values are given only as a typical example. System bootloader mode The embedded bootloader code is located in the system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces.

  • Page 29: Debug Management

    Figure 21. Host to board connection SWJ debug port (serial wire and JTAG) The core of the STM32F7 Series integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It ® is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.

  • Page 30: Pinout And Debug Port Pins

    5.3.1 SWJ debug port pins Five pins are used as outputs from the STM32F7 Series for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages. Table 4. SWJ debug port pins...

  • Page 31: Internal Pull-Up And Pull-Down On Jtag Pins

    AN4661 Debug management Table 5 shows the different possibilities to release some pins. Table 5. Flexible SWJ-DP assignment SWJ IO pin assigned PA14 / PA13 / Available debug ports PA15 / PB3 / PB4 / JTCK / JTMS / JTDI JTDO NJTRST SWCL...

  • Page 32: Swj Debug Port Connection With Standard Jtag Connector

    Debug management AN4661 5.3.4 SWJ debug port connection with standard JTAG connector Figure 22 shows the connection between the STM32F7 Series and a standard JTAG connector. Figure 22. JTAG connector implementation 32/54 DocID027559 Rev 5...

  • Page 33: Recommendations

    AN4661 Recommendations Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to the ground (V ) and another dedicated to the V supply. This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.

  • Page 34: Other Signals

    Recommendations AN4661 Figure 23. Typical layout for V pair Other signals When designing an application, the EMC performance can be improved by closely studying: • Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands).

  • Page 35: Recommendations For The Wlcsp180 Package In The Stm32F769Ax/Stm32F768Ax Devices

    AN4661 Recommendations Recommendations for the WLCSP180 package in the STM32F769Ax/STM32F768Ax devices These recommendations are required for the WLCSP180 package in the STM32F769Ax/STM32F768Ax devices: The NC (not-connected) balls must not be connected to GND nor to VDD. The NC (not-connected) pins are not bounded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid an extra current consumption in low-power modes.

  • Page 36: Reference Design

    Reference design AN4661 Reference design Description The reference design shown in Figure 24, is based on the STM32F756NGH6, a highly ® integrated microcontroller running at 216 MHz, that combines the Cortex -M7 32-bit RISC CPU core with 1 Mbyte of embedded Flash memory and system SRAM up to 320 Kbytes (including Data TCM RAM 64 Kbytes), 16 Kbytes of instruction RAM (ITCM-RAM) and 4 Kbytes of backup SRAM.

  • Page 37: Component References

    AN4661 Reference design Component references Table 6. Mandatory components Component name Reference Quantity Comments Microcontroller STM32F756NGH6 TFBGA216 package Ceramic capacitors Capacitor 100 nF (decoupling capacitors) Ceramic capacitor Capacitor 4.7 µF (decoupling capacitor) Table 7. Optional components Components Reference Quantity Comments name Pull-up and pull-down for JTAG, BOOT pin, PDR and Resistor...

  • Page 38: Figure 24. Stm32F756Ngh6 Reference Schematic

    Reference design AN4661 Figure 24. STM32F756NGH6 reference schematic 38/54 DocID027559 Rev 5...

  • Page 39: Table 8. Reference Connection For All Packages

    AN4661 Reference design Table 8. Reference connection for all packages Pin Name PA13 (JTMS-SWDIO) PA14 (JTCK-SWCLK) PA15 (JTDI) PB3 (JTDO/TRACESWO) PB4 (NJTRST) (1)(2) PC14 (PC14-OSC32_IN) (1)(2) PC15 (PC15-OSC32_OUT) PH0 (PH0-OSC_IN) PH1 (PH1-OSC_OUT) BOOT NRST BYPASS_REG PDR_ON REF+ REF- CAP1 CAP2 DDUSB DocID027559 Rev 5 39/54...
  • Page 40 Reference design AN4661 Table 8. Reference connection for all packages (continued) Pin Name PA0-WKUP PC13 40/54 DocID027559 Rev 5...
  • Page 41 AN4661 Reference design 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF.

  • Page 42: Recommended Pcb Routing Guidelines For Stm32F7 Series Devices

    Recommended PCB routing guidelines for STM32F7 Series devices AN4661 Recommended PCB routing guidelines for STM32F7 Series devices PCB stack-up In order to reduce the reflections on high speed signals, it is necessary to match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.

  • Page 43: Crystal Oscillator

    (AN2867), for further guidance on how to layout and route crystal oscillator circuits. Power supply decoupling An adequate power decoupling for STM32F7 Series is necessary to prevent an excessive power noise and ground bounce noise. Please refer to Section 1.2: Power supply scheme.

  • Page 44: High Speed Signal Layout

    Recommended PCB routing guidelines for STM32F7 Series devices AN4661 Figure 27. Example of bypass cap placed underneath the STM32F7 Series • Place the bypass capacitors as close as possible to the power and ground pins of the MCU. • Add the recommended bypass capacitors for as many V /GND pairs as possible.

  • Page 45: Flexible Memory Controller (Fmc) Interface

    + N*C where Host is Host Card STM32F7 Series, bus is all the signals and Card is SD card. 8.4.2 Flexible memory controller (FMC) interface Interface connectivity The FMC controller and in particular SDRAM memory controller which has many signals, most of them have a similar functionality and work together.

  • Page 46: Quadrature Serial Parallel Interface (Quad-Spi)

    Recommended PCB routing guidelines for STM32F7 Series devices AN4661 Interface signal layout guidelines: • Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND • Trace the impedance: 50Ω ± 10% • The maximum trace length should be below 120mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used •...

  • Page 47: Embedded Trace Macrocell (Etm)

    AN4661 Recommended PCB routing guidelines for STM32F7 Series devices • Avoid using a serpentine routing for the clock signal and as less via(s) as possible for the whole path. a via alters the impedance and adds a reflection to the signal.

  • Page 48: Figure 28. Bga 0.8Mm Pitch Example Of Fan-Out

    Recommended PCB routing guidelines for STM32F7 Series devices AN4661 Figure 28. BGA 0.8mm pitch example of fan-out Figure 29. Via fan-out Figure 30. FMC signal fan-out routing example 48/54 DocID027559 Rev 5...

  • Page 49: Wlcsp143 0.4 Mm Pitch Design Example

    AN4661 Recommended PCB routing guidelines for STM32F7 Series devices 8.5.2 WLCSP143 0.4 mm pitch design example Table 10. Wafer level chip scale package information Package information (mm) Design parameters (mm) Microvia size : hole size ∅= 0.1, via land: 0.2 Bump pitch : 0.4...

  • Page 50: Figure 31. 143-Bumps Wlcsp, 0.40 Mm Pitch Routing Example

    Recommended PCB routing guidelines for STM32F7 Series devices AN4661 Figure 31. 143-bumps WLCSP, 0.40 mm pitch routing example 50/54 DocID027559 Rev 5...

  • Page 51: Conclusion

    AN4661 Conclusion Conclusion This application note should be used as a starting reference for a new design with the STM32F7 Series devices. DocID027559 Rev 5 51/54...

  • Page 52: Revision History

    Figure 13: NRST circuitry timing example. Updated Section 7.1: Description changing the frequency at 216 MHz. Updated whole document with STM32F7 Series Root Part Number. Updated cover page adding reference documents. Added Section 1.1.3: Independent SDMMC2 supply for STM32F767xx/STM32F777xx and STM32F72xxx/STM32F73xxx devices.

  • Page 53: Figure 3. Vddsdmmc Connected To External Power Supply

    Added Figure 8: STM32F7x3xx power supply scheme. 03-Feb-2017 Updated Table 1: Regulator ON/OFF and internal reset ON/OFF availability adding the LQFP64 and WLCSP100 packages and notes. Updated Table 3: STM32F7 Series bootloader communication peripherals adding peripherals. DocID027559 Rev 5 53/54...
  • Page 54 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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