Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1837

DMA LLP High Read Channel Register
The
PCIE_DMARD_LLP_HI_[n]
on. This register value must always be initialized because the default is undefined. All fields marked Reserved must
be programmed to 1'b0. All fields marked Reserved MUST be programmed to 1'b0. This register is not affected by
any of the reset signals.
VALUE[31:16] (R/W)
Upper 32 bits of the address
Figure 29-57: PCIE_DMARD_LLP_HI_[n] Register Diagram
Table 29-66: PCIE_DMARD_LLP_HI_[n] Register Fields
Bit No.
(Access)
31:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is implemented in RAM whose contents are uninitialized after power
15
0
VALUE[15:0] (R/W)
Upper 32 bits of the address
31
0
Bit Name
Upper 32 bits of the address.
The PCIE_DMARD_LLP_HI_[n].VALUE bit field contains the upper 32 bits of
the address of the linked list transfer list in local memory. Used in linked list mode
only. The PCIE_DMARD_LLP_HI_[n].VALUE bit field is updated by the DMA
to point to the next element in the transfer list as elements are consumed.
14 13 12 11 10 9 8 7
0 0 0 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
6 5 4 3 2 1 0
0 0 0 0 0 0 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0
29–133