Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1845

DMA Write Channel Arbitration Weight Low Off Register
The
PCIE_DMAWR_ARBWGT_LO_[n]
that channel before it must return to the arbitration routine. It does this for the 5-bit channel weight (for write
channels 0-3). When the channel weight count is reached, the WWR arbiter selects the next channel to be process-
ed. The software must initialize this register before ringing the doorbell. The value range is (0x00-0x1F) correspond-
ing to (1-32) transactions.
Figure 29-65: PCIE_DMAWR_ARBWGT_LO_[n] Register Diagram
Table 29-74: PCIE_DMAWR_ARBWGT_LO_[n] Register Fields
Bit No.
(Access)
4:0 CH0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register specifies the number of TLP requests that the DMA can issue for
15 14 13 12
1 0 0
CH0 (R/W)
Channel 0 Weight
31 30 29 28
0 0 0
Bit Name
Channel 0 Weight.
The PCIE_DMAWR_ARBWGT_LO_[n].CH0 bit field value is used by the channel
weighted round robin arbiter to select the next channel read request. The weight is ini-
tialized by software before ringing the doorbell.
11 10 9 8 7 6 5
0 0 1 0 0 0 0 1
27 26 25 24 23 22 21 20
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PCIE Register Descriptions
4 3 2 1 0
0 0 0 0 1
19 18 17 16
0 0 0 0 0
29–141