Tim1&Tim8 Counter (Timx_Cnt); Tim1&Tim8 Prescaler (Timx_Psc); Tim1&Tim8 Auto-Reload Register (Timx_Arr) - ST STM32F446 Series Reference Manual

Advanced-control timers (TIM1&TIM8)
Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels
depends on the OCx and OCxN channel state and the GPIO registers.
16.4.10 TIM1&TIM8 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CNT[15:0]: Counter value
16.4.11 TIM1&TIM8 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
16.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
512/1328
12 11 10 9
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12 11 10 9
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The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
rw rw rw rw
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 16.3.1: Time-base unit
The counter is blocked while the auto-reload value is null.
8 7 6
CNT[15:0]
rw rw rw
8 7 6
PSC[15:0]
rw rw rw
8 7 6
ARR[15:0]
rw rw rw
for more details about ARR update and behavior.
RM0390 Rev 4
5 4 3 2
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5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
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RM0390
1 0
rw rw
1 0
rw rw
1 0
rw rw