Adc Common Status Register (Adc_Csr); Adc Common Control Register (Adc_Ccr) - ST STM32F205 series Reference Manual

Analog-to-digital converter (ADC)

10.13.15 ADC Common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing it to 0 in the corresponding ADC_SR register.
31 30 29 28
15 14 13 12
OVR2 STRT2
Reserved
r
Bits 31:22 Reserved, must be kept at reset value.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
Bit 4 STRT1: Regular channel Start flag of ADC1
Bit 3 JSTRT1: Injected channel Start flag of ADC1
Bit 2 JEOC1: Injected channel end of conversion of ADC1
Bit 1 EOC1: End of conversion of ADC1
Bit 0 AWD1: Analog watchdog flag of ADC1

10.13.16 ADC common control register (ADC_CCR)

Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
DMA[1:0] DDS
Res.
rw rw rw
250/1378
27 26 25
Reserved
11 10 9
JSTRT
JEOC2 EOC2
2
ADC2
r r r r
This bit is a copy of the OVR bit in the ADC1_SR register.
This bit is a copy of the STRT bit in the ADC1_SR register.
This bit is a copy of the JSTRT bit in the ADC1_SR register.
This bit is a copy of the JEOC bit in the ADC1_SR register.
This bit is a copy of the EOC bit in the ADC1_SR register.
This bit is a copy of the AWD bit in the ADC1_SR register.
27 26 25
Reserved
11 10 9
DELAY[3:0]
rw rw rw
24 23 22
OVR3
8 7 6
AWD2 OVR1
Reserved
r
24 23 22
TSVREFE VBATE
rw rw
8 7 6
Reserved
rw
RM0033 Rev 8
21 20 19 18
STRT3 JSTRT3 JEOC 3 EOC3
ADC3
r r r r
5 4 3 2
STRT1 JSTRT1 JEOC 1 EOC1
ADC1
r r r r
21 20 19 18
Reserved
5 4 3 2
MULTI[4:0]
rw rw rw
RM0033
17 16
AWD3
r r
1 0
AWD1
r r
17 16
ADCPRE
rw rw
1 0
rw rw