Adc Regular Data Register (Adc_Dr); Adc Common Status Register (Adc_Csr) - ST STM32F410 Reference Manual

RM0401
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data

11.12.14 ADC regular data register (ADC_DR)

Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data

11.12.15 ADC Common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of ADC1. Nevertheless it is read-only and
does not allow to clear the different status bits. Instead each status bit must be cleared by
writing it to 0 in the corresponding ADC_SR register.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
Bit 4 STRT1: Regular channel Start flag of ADC1
Bit 3 JSTRT1: Injected channel Start flag of ADC1
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in
27 26 25
Res. Res. Res.
11 10 9
r r r r
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in
Figure 37.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit is a copy of the OVR bit in the ADC1_SR register.
This bit is a copy of the STRT bit in the ADC1_SR register.
This bit is a copy of the JSTRT bit in the ADC1_SR register.
Figure 36
24 23 22
Res. Res. Res. Res.
8 7 6
DATA[15:0]
r r r
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res. OVR1
RM0401 Rev 3
Analog-to-digital converter (ADC)
and Figure 37.
21 20 19 18
Res. Res. Res.
5 4 3 2
r r r r
Figure 36
21 20 19 18
Res. Res. Res.
5 4 3 2
STRT1 JSTRT1 JEOC 1 EOC1
r r r r
17 16
Res. Res.
1 0
r r
and
17 16
Res. Res.
1 0
AWD1
r r
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