Dma Stream X Configuration Register (Dma_Sxcr) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus
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Direct memory access controller (DMA)
Bits 24, 18, 8, 2 CDMEIF[7:4]: stream x clear direct mode error interrupt flag (x = 7..4)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIF[7:4]: stream x clear FIFO error interrupt flag (x = 7..4)
9.5.5

DMA stream x configuration register (DMA_SxCR)

This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 * x, (x = 0 to 7)
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
15
14
13
PINCOS
MSIZE[1:0]
rw
rw
rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:25 CHSEL[3:0]: channel selection
Bits 24:23 MBURST[1:0]: memory burst transfer configuration
238/1324
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register.
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register.
28
27
26
25
CHSEL[3:0]
rw
rw
rw
rw
12
11
10
9
PSIZE[1:0]
MINC
PINC
rw
rw
rw
rw
These bits are set and cleared by software.
0000: channel 0 selected
0001: channel 1 selected
0010: channel 2 selected
0011: channel 3 selected
0100: channel 4 selected
0101: channel 5 selected
0110: channel 6 selected
0111: channel 7 selected
1000: channel 8 selected
1001: channel 9 selected
1010: channel 10 selected
1011: channel 11 selected
1100: channel 12 selected
1101: channel 13 selected
1110: channel 14 selected
1111: channel 15 selected
These bits are protected and can be written only if EN is '0'.
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is '0'.
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.
24
23
22
21
MBURST[1:0]
PBURST[1:0]
rw
rw
rw
rw
8
7
6
5
CIRC
DIR[1:0]
PFCTRL
rw
rw
rw
rw
RM0430 Rev 8
20
19
18
Res.
CT
DBM
rw
rw
4
3
2
TCIE
HTIE
TEIE
DMEIE
rw
rw
rw
RM0430
17
16
PL[1:0]
rw
rw
1
0
EN
rw
rw

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