Dma Stream X Configuration Register (Dma_Sxcr) (X = 0 - ST STM32F205 series Reference Manual

RM0033
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)
9.5.5

DMA stream x configuration register (DMA_SxCR) (x = 0..7)

This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 × stream number
Reset value: 0x0000 0000
31 30 29
Reserved
15 14 13
PINCOS MSIZE[1:0]
rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:25 CHSEL[2:0]: Channel selection
Bits 24:23 MBURST: Memory burst transfer configuration
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
Bit 20 Reserved, must be kept at reset value.
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register
28 27 26 25
CHSEL[2:0]
rw rw rw
12 11 10 9
PSIZE[1:0] MINC PINC
rw rw rw rw
These bits are set and cleared by software.
000: channel 0 selected
001: channel 1 selected
010: channel 2 selected
011: channel 3 selected
100: channel 4 selected
101: channel 5 selected
110: channel 6 selected
111: channel 7 selected
These bits are protected and can be written only if EN is '0'
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is '0'
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is '0'
In direct mode, these bits are forced to 0x0 by hardware.
24 23 22 21
MBURST [1:0] PBURST[1:0]
rw rw rw rw
8 7 6 5
CIRC DIR[1:0] PFCTRL
rw rw rw rw
RM0033 Rev 8
DMA controller (DMA)
20 19 18
CT DBM
Reser-
ved
rw rw
4 3 2
TCIE HTIE TEIE DMEIE
rw rw rw
17 16
PL[1:0]
rw rw
1 0
EN
rw rw
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