Power Control Registers; Pwr Power Control Register (Pwr_Cr) - ST STM32F410 Reference Manual

Power controller (PWR)
4.4

Power control registers

4.4.1

PWR power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 8000 (reset by wakeup from Standby mode)
31 30 29
Res. Res. Res.
15 14 13
VOS ADCDC1
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Bits 31:22 Reserved, must be kept at reset value.
Bit 21 FISSR: Flash Interface Stop while System Run
0: Flash Interface clock run (Default value).
1: Flash Interface clock off.
Note: This bit could not be set while executing with the Flash itself. It should be done with
Bit 20 FMSSR: Flash Memory Sleep System Run.
0: Flash standard mode (Default value)
1: Flash forced to be in STOP or Deep-power down mode (depending of FPDS value bit) by
hardware.
Note: This bit could not be set while executing with the Flash itself. It should be done with
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
These bits control the main internal voltage regulator output voltage to achieve a trade-off
between performance and power consumption when the device does not operate at the
maximum frequency (refer to the corresponding datasheet for more details).
These bits can be modified only when the PLL is OFF. The new value programmed is active
only when the PLL is ON. When the PLL is OFF, the voltage regulator is set to scale 3
independently of the VOS register content.
00: Reserved (Scale 3 mode selected)
01: Scale 3 mode <= 64 MHz
10: Scale 2 mode (reset value) <= 84 MHz
11: Scale 1 mode <= 100 MHz
Bit 13 ADCDC1:
0: No effect.
1: Refer to AN4073 for details on how to use this bit.
Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when
86/771
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
MRLV LPLV
Res. FPDS
DS DS
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specific routine executed from RAM.
specific routine executed from RAM.
the Prefetch is OFF.
24 23 22
Res. Res. Res. FISSR FMSSR
8 7 6
DBP PLS[2:0]
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RM0401 Rev 3
21 20 19 18
Res. Res.
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5 4 3 2
PVDE CSBF CWUF
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RM0401
17 16
Res. Res.
1 0
PDDS LPDS
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