18.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register
Offset
0x038
Reset
Access
Name
Bit
Name
31
RXENAT1
Set to enable reception after transmission.
30
TXDISAT1
Set to disable transmitter and release data bus directly after transmission.
29
TXBREAK1
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of USARTn_TXDATA.
28
TXTRIAT1
Set to tristate transmitter by setting TXTRI after transmission.
27
UBRXAT1
Set clear RXBLOCK after transmission, unblocking the receiver.
26:25
Reserved
24:16
TXDATA1
Second frame to write to FIFO.
15
RXENAT0
Set to enable reception after transmission.
14
TXDISAT0
Set to disable transmitter and release data bus directly after transmission.
13
TXBREAK0
Set to send data as a break. Recipient will see a framing error or a break condition depending on its configuration and the
value of TXDATA.
12
TXTRIAT0
Set to tristate transmitter by setting TXTRI after transmission.
11
UBRXAT0
Set clear RXBLOCK after transmission, unblocking the receiver.
10:9
Reserved
8:0
TXDATA0
First frame to write to buffer.
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset
Access
Description
0
W
Enable RX After Transmission
0
W
Clear TXEN After Transmission
0
W
Transmit Data as Break
0
W
Set TXTRI After Transmission
0
W
Unblock RX After Transmission
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x000
W
TX Data
0
W
Enable RX After Transmission
0
W
Clear TXEN After Transmission
0
W
Transmit Data as Break
0
W
Set TXTRI After Transmission
0
W
Unblock RX After Transmission
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x000
W
TX Data
Bit Position
Reference Manual
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 580
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