Prs_Chx_Ctrl - Channel Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

15.5.11 PRS_CHx_CTRL - Channel Control Register

Offset
0x050
Reset
Access
Name
Bit Name
31 Reserved
30 ASYNC
Set to enable asynchronous mode of this reflex signal
29 Reserved
28 ANDNEXT
If set, channel output is AND'ed with the next channel output
27 ORPREV
If set, channel output is OR'ed with the previous channel output
26 INV
If set, channel output is inverted
25 STRETCH
If set, stretches channel output to ensure that the target clock domain sees it.
24:22 Reserved
21:20 EDSEL
Select edge detection.
Value
0
1
2
3
19:15 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Asynchronous Reflex
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW And Next
0 RW Or Previous
0 RW Invert Channel
0 RW Stretch Channel Output
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Edge Detect Select
Mode Description
OFF Signal is left as it is
POSEDGE A one HFCLK cycle pulse is generated for every positive edge of the
incoming signal
NEGEDGE A one HFCLK clock cycle pulse is generated for every negative edge of
the incoming signal
BOTHEDGES A one HFCLK clock cycle pulse is generated for every edge of the in-
coming signal
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
Reference Manual
PRS - Peripheral Reflex System
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 440