Prs Outputs - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

23.3.14.3 Overflow/Underflow
If CHxDATA is written to while CHxBL is cleared, the channel overflow flag (CHxOF) will be set. If a new conversion is triggered (e.g. via
PRS) before data is written to CHxDATA (CHxDATA is empty) the channel underflow flag (CHxUF) will be set.
23.3.14.4 EM2/3 Sleep Error
The VDAC can only operate in EM2/3 when DACCLKMODE is set to ASYNC. If EM2 or EM3 is entered while a channel is enabled and
DACCLKMODE is set to SYNC the EM23ERRIF flag will be set.

23.3.15 PRS Outputs

The VDAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when the corresponding channel has finished a
conversion. Only available when DACCLKMODE is set to SYNC.
23.3.16 DMA Request
Each channel sends a DMA request when there is space in the channel's data register (VDACn_CHxDATA). These registers are initially
empty and also become empty every time a conversion is triggered. The request is cleared when VDACn_CHxDATA is written.
23.3.17 LESENSE Trigger Mode
The VDAC can be controlled by LESENSE by programming the TRIGMODE field in VDACn_CHxCTRL to LESENSE. In LESENSE
mode the conversion data can come from either VDACn_CHxDATA registers or LESENSE registers, depending on the LESENSE con-
figuration. The trigger events are also controlled by the LESENSE state machine. See the LESENSE chapter for more information.
23.3.18 Opamps
The VDAC includes a set of highly configurable opamps that can be accessed with the VDAC registers. OPA0 and OPA1 is used for the
output stages of the two VDAC channels, but can be used as standalone opamps if the VDAC channels are not in use. Opamps with
higher numbers are completely standalone. For a detailed description see the OPAMP chapter.
23.3.19 Calibration
The VDAC contains a calibration register, VDACn_CAL, where calibration values for both offset and gain correction can be written. The
required (gain) calibration values depend on the chosen reference and on whether the main or alternative VDAC output is used. The
Device Information page provides the required trim values depending on reference choice and output selection in the DEVIN-
FO_VDACnMAINCAL, DEVINFO_VDACnALTCAL, and DEVINFO_VDACnCH1CAL locations.
The OPAMPs contain a calibration register, VDACn_OPAx_CAL, where calibration values for both offset and gain correction can be
written. The required calibration settings depend on the chosen DRIVESTRENGTH. The required calibration values can be found in the
Device Information pages. For a given OPAMP x, the calibration settings for DRIVESTRENGTH n can be found in DEVINFO_OPAx-
CALn.
23.3.19.1 Channel 1 Calibration
For channel 1, the factory calibration values are only accurate for the main output. When using the alternative outputs or APORT, the
error on the output may be larger than the data sheet values (even when loading values from DEVINFO_VDACn_ALTCAL). To get ac-
curate output from channel 1, either use the main output or perform manual calibration.
23.3.19.2 Manual Calibration
To manually calibrate the VDAC:
1. Enable CH0 and CH1 in their desired modes
2. Set both channel outputs to 80% of full-scale by setting VDACn_CHxDATA = 0xCCC
3. Measure CH0 output and sweep VDACn_CAL.GAINERRTRIM until the smallest calibration error is found
4. Measure CH1 output and sweep VDACn_CAL.GAINERRTRIMCH1 until the smallest calibration error is found
The calibration error is given by
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