Interrupts, Prs Output - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.3.11 Interrupts, PRS Output

The single and scan modes have separate SINGLE and SCAN interrupt flags indicating whether corresponding FIFO contains DVL # of
valid conversion data. Corresponding interrupt enable bit has to be set in ADCn_IEN in order to generate interrupts. For these inter-
rupts, there is no software clear mechanism by writing to ADCn_IFC. The user needs to read enough data from the interrupted FIFO to
ensure it contains less than DVL # of elements. The ADCn_SINGLEFIFOCOUNT/ADCn_SCANFIFOCOUNT can provide number of
valid elements remaining in corresponding FIFO. The FIFO can also be cleared by ADCn_SINGLEFIFOCLEAR/ADCn_SCANFIFO-
CLEAR, but any existing data will be lost by this operation.
In addition to the SINGLE and SCAN interrupt flags, there is separate scan and single channel result overflow interrupt flag which sig-
nals that a result from a scan or single channel FIFO has been overwritten before being read. There is also separate scan and single
channel result underflow interrupt flag which signals that a FIFO read was issued when the FIFO was empty.
There is separate scan and single compare interrupt flag which signals a compare match with latest sample if the CMPEN in
ADCn_SINGLECTRL/ADCn_SCANCTRL is enabled.
ADC has two separate PRS outputs, one for single channel and one for scan sequence. A finished conversion results in a one
ADC_CLK cycle pulse, which is output to the Peripheral Reflex System (PRS). Note that the PRS pulse for scan is generated once after
every channel conversion in the scan sequence.
26.3.12 DMA Request
The ADC has two DMA request lines, SINGLEREQ and SCANREQ, which are set when a single or scan FIFO receives DVL# of sam-
ples. The requests are cleared when the corresponding single or scan result register is read and corresponding FIFO count reaches
lower than DVL. It also has two additional DMA Single request lines, SINGLESREQ and SCANSREQ, that are set when the corre-
sponding FIFO is not empty.
26.3.13 Calibration
The ADC supports offset and gain calibration to correct errors due to process and temperature variations. This must be done individual-
ly for each reference used. For each reference, it needs to be repeated for single-ended, negative single-ended (see
lection for details) and differential measurement. The ADC calibration (ADCn_CAL) register contains register fields for calibrating offset
and gain for both single and scan mode. The gain and offset calibration are done in single channel mode, but the resulting calibration
values can be used for both single and scan mode.
Gain and offset for various references and modes are calibrated during production and the calibration values for these can be found in
the Device Information page. During reset, the gain and offset calibration registers are loaded with the production calibration values for
the 1V25 reference. Others can be loaded as needed or the user can perform calibration on the fly using the particular reference and
mode to be used and write the result in the ADCn_CAL before starting the ADC conversion with them.
26.3.13.1 Offset Calibration
Offset calibration must be performed prior to gain calibration. Follow these steps for the offset calibration in single mode:
1. Select the desired full scale configuration by setting the REF bit field of the ADCn_SINGLECTRL register.
2. Set the AT bit field of the ADCn_SINGLECTRL register to 16CYCLES.
3. Set the POSSEL and NEGSEL of the ADCn_SINGLECTRL register to VSS, and set the DIFF to 1 for enabling differential input if
calibrating for DIFF measurement. During calibration, the ADC samples represent the code coming out of the analog. Thus, since
the input voltage is 0, the expected ADC output is 0b100000000000 in differential mode, 0b000000000000 in single-ended mode
and 0b111111111111 in negative single-ended mode.
4. A binary search is used to find the offset calibration value. Set the CALEN to 1, and OFFSETINVMODE to 1 (if calibrating for nega-
tive single-ended conversion) in the ADCn_CAL register. If user is performing negative single-ended calibration, the SINGLEOFF-
SETINV provides the offset else SINGLEOFFSET bit provides the offset (for both single-ended and differential offset calibration).
Start with 0b0000 (or 0b1111 if doing calibration for differential mode) in SINGLEOFFSET or with 0b1000 in SINGLEOFFSETINV (if
calibrating for negative single-ended conversion). Set the SINGLESTART bit in the ADCn_CMD register to perform a 12-bit conver-
sion and read the ADCn_SINGLEDATA register. The offset is (ADCn_SINGLEDATA - expected ADC output). Calculate this and
write [3:0] of the result into SINGLEOFFSET or SCANOFFSETINV (if doing negative single-ended conversion). The user repeats
till ADCn_SINGLEDATA matches expected ADC output. The ADC has a 8LSB built in negative offset to allow for negative offset
correction. So, with default offset value, which corrects for the negative offset, the converted ADCn_SINGLEDATA would match
expected ADC output if there were no offset. To get better noise immunity, the sampling phase can be repeated with Oversampling
enabled. The result of the binary search is written to the SINGLEOFFSET (or SINGLEOFFSETINV) field of the ADCn_CAL regis-
ter.
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ADC - Analog to Digital Converter
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