4.7.42 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3
Offset
0x178
Access
Name
Bit
Name
31:24
3V0LPATT1LPCMPBIAS3
23:16
1V8LPATT1LPCMPBIAS3
15:8
3V0LPATT1LPCMPBIAS2
7:0
1V8LPATT1LPCMPBIAS2
4.7.43 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0
Offset
0x17C
Access
Name
Bit
Name
31:16
Reserved
15:8
LPCMPHYSSELLPATT1
7:0
LPCMPHYSSELLPATT0
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Bit Position
Access
Description
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=3
RO
DCDC LPVREF Trim for 3.0V output, LPATT=1, LPCMPBIAS=3
RO
DCDC LPVREF Trim for 1.8V output, LPATT=1, LPCMPBIAS=2
Bit Position
Access
Description
Reserved for future use
RO
DCDC LPCMPHYSSEL Trim, LPATT=1
RO
DCDC LPCMPHYSSEL Trim, LPATT=0
Reference Manual
Memory and Bus System
Rev. 1.1 | 93
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