Ldma_Status - Dma Status Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

8.6.2 LDMA_STATUS - DMA Status Register

Offset
0x004
Reset
Access
Name
Bit Name
31:29 Reserved
28:24 CHNUM
The value of CHNUM always reads the total number of channels present for this instance of the DMA controller module.
23:21 Reserved
20:16 FIFOLEVEL
The value of FIFOLEVEL indicates the number of entries currently in the FIFO. (Note when all channels are disabled, this
register will read the total number of entries in the FIFO.)
15:11 Reserved
10:8 CHERROR
When the ERROR flag is set in the LDMA_IF register, the CHERROR field will indicate the most recent channel to have a
transfer error.
7:6 Reserved
5:3 CHGRANT
The value of this field indicates the currently active channel or last active channel. Note that the reset value for this field is
zero.
2 Reserved
1 ANYREQ
The value of this bit will be TRUE (1) if any requests are pending
0 ANYBUSY
The value of this bit will be TRUE (1) if one or more DMA channels are actively transferring data
silabs.com | Building a more connected world.
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x08 R Number of Channels
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x10 R FIFO Level
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 R Errant Channel Number
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 R Granted Channel Number
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R Any DMA Channel Request Pending
0 R Any DMA Channel Busy
Bit Position
Reference Manual
LDMA - Linked DMA Controller
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 181