Register Description; Cmu_Ctrl - Cmu Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5 Register Description

11.5.1 CMU_CTRL - CMU Control Register

Offset
0x000
Reset
Access
Name
Bit Name
31:22 Reserved
21 HFRADIOCLKEN
Set to enable the HFRADIOCLK.
20 HFPERCLKEN
Set to enable the HFPERCLK.
19:17 Reserved
16 WSHFLE
Set to allow access to LE peripherals when running HFBUSCLK
15:10 Reserved
9:5 CLKOUTSEL1
Controls the clock output 1 multiplexer. To actually output on the pin, set CLKOUT1PEN in CMU_ROUTE.
Value
0
1
2
3
6
7
9
10
11
12
13
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
1 RW HFRADIOCLK Enable
1 RW HFPERCLK Enable
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Wait State for High-Frequency LE Interface
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW Clock Output Select 1
Mode Description
DISABLED Disabled
ULFRCO ULFRCO (directly from oscillator)
LFRCO LFRCO (directly from oscillator)
LFXO LFXO (directly from oscillator)
HFXO HFXO (directly from oscillator)
HFEXPCLK HFEXPCLK
ULFRCOQ ULFRCO (qualified)
LFRCOQ LFRCO (qualified)
LFXOQ LFXO (qualified)
HFRCOQ HFRCO (qualified)
AUXHFRCOQ AUXHFRCO (qualified)
Bit Position
at frequencies higher than 32 MHz
LE
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
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