Bit
Name
5
RXDATAV
Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.
4
TXBL
Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.
3
TXC
Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.
2
ADDR
Set when incoming address is accepted, i.e. own address or general call address is received.
1
RSTART
Set when a repeated start condition is detected.
0
START
Set when a start condition is successfully transmitted.
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Reset
Access
Description
0
R
Receive Data Valid Interrupt Flag
1
R
Transmit Buffer Level Interrupt Flag
0
R
Transfer Completed Interrupt Flag
0
R
Address Interrupt Flag
0
R
Repeated START Condition Interrupt Flag
0
R
START Condition Interrupt Flag
Reference Manual
I2C - Inter-Integrated Circuit Interface
Rev. 1.1 | 516
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