Register Description; Usartn_Ctrl - Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.5 Register Description

18.5.1 USARTn_CTRL - Control Register

Offset
0x000
Reset
Access
Name
Bit Name
31 SMSDELAY
Delay Synchronous Master sample point to the next setup edge to improve timing and allow communication at higher
speeds
30 MVDIS
Disable majority vote for 16x, 8x and 6x oversampling modes.
29 AUTOTX
Transmits as long as RX is not full. If TX is empty, underflows are generated.
28 BYTESWAP
Set to switch the order of the bytes in double accesses.
Value
0
1
27:26 Reserved
25 SSSEARLY
Setup data on sample edge in synchronous slave mode to improve MOSI setup time
24 ERRSTX
When set, the transmitter is disabled on framing and parity errors (asynchronous mode only) in the receiver.
Value
0
1
23 ERRSRX
When set, the receiver is disabled on framing and parity errors (asynchronous mode only).
Value
0
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
0 RW Synchronous Master Sample Delay
0 RW Majority Vote Disable
0 RW Always Transmit When RX Not Full
0 RW Byteswap in Double Accesses
Description
Normal byte order
Byte order swapped
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Synchronous Slave Setup Early
0 RW Disable TX on Error
Description
Received framing and parity errors have no effect on transmitter
Received framing and parity errors disable the transmitter
0 RW Disable RX on Error
Description
Framing and parity errors have no effect on receiver
Bit Position
Reference Manual
1.2 Conven-
Rev. 1.1 | 562