Suppressed Conditional Branch Target Prefetch (Scbtp); Cortex-M4 If-Then Block Folding - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

Reference Manual
MSC - Memory System Controller

7.3.9 Suppressed Conditional Branch Target Prefetch (SCBTP)

MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-M4 conditional branch target
prefetches. Normally, the Cortex-M4 core prefetches both the next sequential instruction and the instruction at the branch target ad-
dress when a conditional branch instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one
extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is taken or not. To optimize for
low energy, the MSC can be configured to cancel these speculative branch target prefetches. With this configuration, energy consump-
tion is more optimal, as the branch target instruction fetch is delayed until the branch condition is evaluated.
The performance penalty with this mode enabled is source code dependent, but is normally less than 1% for core frequencies from 26
MHz and below. To enable the mode at frequencies from 26 MHz and below write WS0SCBTP to the MODE field of the
MSC_READCTRL register. For frequencies above 26 MHz, use the WS1SCBTP mode, and for frequencies above 40 MHz, use the
WS2SCBTP mode. An increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode. The perform-
ance penalty in WS1SCBTP/WS2SCBTP mode depends greatly on the density and organization of conditional branch instructions in
the code.

7.3.10 Cortex-M4 If-Then Block Folding

The Cortex-M4 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks
are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cy-
cles. With this scheme, performance is optimized at the cost of higher energy consumption as the processor fetches more instructions
from memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary Control Register; see
the Cortex-M4 Technical Reference Manual for details. Normally, it is expected that this feature is most efficient at core frequencies
above 26 MHz. Folding is enabled by default.
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