11.5.39 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg)
When waking up from EM4 make sure EM4UNLATCH in EMU_CMD is set for this to take effect
Offset
0x130
Reset
Access
Name
Bit
Name
31:2
Reserved
1:0
RTCC
Configure Real-Time Counter and Calendar prescaler
Value
0
1
2
11.5.40 CMU_HFRADIOALTPRESC - High Frequency Alternate Radio Peripheral Clock Prescaler Register
Offset
0x138
Reset
Access
Name
Bit
Name
31:17
Reserved
16:8
PRESC
Specifies the clock divider for the HFRADIOALTCLK (relative to HFCLK).
Value
PRESC
7:0
Reserved
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
RW
Real-Time Counter and Calendar Prescaler
Mode
Description
DIV1
LFECLK
DIV2
LFECLK
DIV4
LFECLK
Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x000
RW
HFRADIOALTCLK Prescaler
Description
Clock division factor of PRESC+1.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
= LFECLK
RTCC
= LFECLK/2
RTCC
= LFECLK/4
RTCC
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 353
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