Letimern_Rep1 - Repeat Counter Register 1 (Async Reg); Letimern_If - Interrupt Flag Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

21.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg)

For more information about asynchronous registers see
Offset
0x01C
Reset
Access
Name
Bit Name
31:8 Reserved
7:0 REP1
Optional repeat counter or buffer for REP0.

21.5.9 LETIMERn_IF - Interrupt Flag Register

Offset
0x020
Reset
Access
Name
Bit Name
31:5 Reserved
4 REP1
Set when repeat counter 1 reaches zero.
3 REP0
Set when repeat counter 0 reaches zero or when the REP1 interrupt flag is loaded into the REP0 interrupt flag.
2 UF
Set on LETIMER underflow.
1 COMP1
Set when LETIMER reaches the value of COMP1.
0 COMP0
Set when LETIMER reaches the value of COMP0.
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4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RWH Repeat Counter 1
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 R Repeat Counter 1 Interrupt Flag
0 R Repeat Counter 0 Interrupt Flag
0 R Underflow Interrupt Flag
0 R Compare Match 1 Interrupt Flag
0 R Compare Match 0 Interrupt Flag
Bit Position
Bit Position
Reference Manual
LETIMER - Low Energy Timer
Registers).
1.2 Conven-
1.2 Conven-
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