Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 163

Arbslot order 8
Arbslot1
Arbslot2
Arbslot4
Arbslot8 1
The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta-
tion of the arbitration order.
For example, if we have one low latency channel (CHNL0) and two latency tolerant channels (CHNL1 and CHNL2). We could use the
following settings.
LDMA_CTRL.NUMFIXED = 0; set round robin for all channels.
CHNL0_CFG.ARBSLOTS = TWO;
CHNL1_CFG.ARBSLOTS = ONE;
CHNL2_CFG.ARBSLOTS = ONE;
If all channels are constantly requesting transfers, then the arbitration order is: CHNL0, CHNL1, CHNL0, CHNL2, CHNL0, CHNL1,
CHNL0, CHNL2, CHNL0, etc
Note, there are no channels assigned to arbitration slot four or eight in this example, so those slots are skipped and the final sequence
is ARBSLOT2, ARBSLOT1, ARBSLOT2, ARBSLOT1, etc...
Channel 1 and Channel 2 are selected in round robin order when arbitration slot 1 is executed.
If we replace the ARBSLOTS value for channel 0 with EIGHT, then the sequence would look like the following:
CHNL0, CHNL0, CHNL0, CHNL0, CHNL1, CHNL0, CHNL0, CHNL0, CHNL2, CHNL0, CHNL0, CHNL0, CHNL0, CHNL1, etc.
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Table 8.1. Arbitration Slot Order
4 8 2 8
1
1
1 1
4 8 1 8
1
1
1 1
Reference Manual
LDMA - Linked DMA Controller
4 8 2 8
1
1
1 1
Rev. 1.1 | 163
4
1