Functional Description; Ppu - Peripheral Protection Unit - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

12.3 Functional Description

An overview of the SMU module within the system is shown in

12.3.1 PPU - Peripheral Protection Unit

The number of peripheral memory regions on the device exceeds the number of configurable regions available using the MPU. While it
is possible to manage finer granularity of memory security through software, the PPU provides a hardware solution for fine-grained pe-
ripheral-level protection to eliminate the performance degradation associated with a partially software-managed solution.
The PPU provides a hardware access barrier to any peripheral that is configured to be protected. When an attempt is made to access a
peripheral without the required privilege level, the PPU detects the fault and intercepts the access. No write or read of the peripheral
register space occurs, and an all-zero value is returned if the access is a read. See
cess faults are reported to the CPU.
Note: The CPU is the only system bus master in the EFR32 that can trigger access faults. All other masters are given full access privi-
leges and have no configurable context switching enabled.
silabs.com | Building a more connected world.
Figure 12.1 Bus-Level Security System View on page
IRQs
ARM Core
Control/Status
MPU
PPU
Bus Matrix
Figure 12.1. Bus-Level Security System View
SMU - Security Management Unit
SMU
Memory Space
Peripherals
SRAM
Code
12.3.2.2 PPU Control
Reference Manual
365.
for more details on how ac-
Rev. 1.1 | 365