Adcn_Singlectrl - Single Channel Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.5.4 ADCn_SINGLECTRL - Single Channel Control Register

Offset
0x010
Reset
Access
Name
Bit Name
31 CMPEN
Enable/disable Compare Logic
Value
0
1
30 Reserved
29 PRSEN
Enabled/disable PRS trigger of single channel.
Value
0
1
28 Reserved
27:24 AT
Select the acquisition time for single channel.
Value
0
1
2
3
4
5
6
7
8
9
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Reset Access Description
0 RW Compare Logic Enable for Single Channel
Description
Disable Compare Logic.
Enable Compare Logic.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Single Channel PRS Trigger Enable
Description
Single channel is not triggered by PRS input.
Single channel is triggered by PRS input selected by PRSSEL.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Single Channel Acquisition Time
Mode Description
1CYCLE 1 conversion clock cycle acquisition time for single channel
2CYCLES 2 conversion clock cycles acquisition time for single channel
3CYCLES 3 conversion clock cycles acquisition time for single channel
4CYCLES 4 conversion clock cycles acquisition time for single channel
8CYCLES 8 conversion clock cycles acquisition time for single channel
16CYCLES 16 conversion clock cycles acquisition time for single channel
32CYCLES 32 conversion clock cycles acquisition time for single channel
64CYCLES 64 conversion clock cycles acquisition time for single channel
128CYCLES 128 conversion clock cycles acquisition time for single channel
256CYCLES 256 conversion clock cycles acquisition time for single channel
Bit Position
Reference Manual
ADC - Analog to Digital Converter
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 878