Emu_Dcdclnvctrl - Dcdc Low Noise Voltage Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

10.5.20 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register

Offset
0x05C
Reset
Access
Name
Bit Name
31:15 Reserved
14:8 LNVREF
Low noise mode Vref trim. LNATT and LNVREF set the output of the DCDC to 3*(1+LNATT)*(235.48+3.226*LNVREF).
Customers should use the emlib functions for configuring this field. Reset with POR, Hard Pin Reset, or BOD Reset.
7:2 Reserved
1 LNATT
Low noise mode feedback attenuation. Customers should use the emlib functions for configuring this field. Reset with POR,
Hard Pin Reset, or BOD Reset.
Value
0
1
0 Reserved
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Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x71 RWH Low Noise Mode VREF Trim
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Low Noise Mode Feedback Attenuation
Mode Description
DIV3 Feedback Ratio is 1/3
DIV6 Feedback Ratio is 1/6
To ensure compatibility with future devices, always write bits to 0. More information in
tions
Bit Position
Reference Manual
EMU - Energy Management Unit
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