6.5 Register Description
6.5.1 AAP_CMD - Command Register
Offset
0x000
Reset
Access
Name
Bit
Name
31:2
Reserved
1
SYSRESETREQ
A system reset request is generated when set to 1. This register is write enabled from the AAP_CMDKEY register.
0
DEVICEERASE
When set, all data and program code in the main block is erased, the SRAM is cleared and then the Lock Bit (LB) page is
erased. This also includes the Debug Lock Word (DLW), causing debug access to be enabled after the next reset. The in-
formation block User Data page (UD) is left unchanged, but the User data page Lock Word (ULW) is erased. This register is
write enabled from the AAP_CMDKEY register.
6.5.2 AAP_CMDKEY - Command Key Register
Offset
0x004
Reset
Access
Name
Bit
Name
31:0
WRITEKEY
The key value must be written to this register to write enable the AAP_CMD register.
Value
0xCFACC118
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0
W1
System Reset Request
0
W1
Erase the Flash Main Block, SRAM and Lock Bits
Reset
Access
Description
0x00000000
W1
CMD Key Register
Mode
Description
WRITEEN
Enable write to AAP_CMD
Bit Position
Bit Position
Reference Manual
DBG - Debug Interface
1.2 Conven-
Rev. 1.1 | 120
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