Bus States; Slave Operation - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

17.3.8 Bus States

The I2Cn_STATE register can be used to determine which state the I
consists of the STATE bit-field, which shows which state the I
which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I
ware response.
The possible values of the STATE field are summarized in
2
I C module is not a part of any ongoing transmission. The remaining status bits in the I2Cn_STATE register are listed in
Transmission Status on page
Mode Value
IDLE 0
WAIT 1
START 2
ADDR 3
ADDRACK 4
DATA 5
DATAACK 6
Bit
BUSY
MASTER
TRANSMITTER
BUSHOLD
NACK
Note:
I2Cn_STATE reflects the internal state of the I
BUSHOLD in I2Cn_STATUS is set.

17.3.9 Slave Operation

2
The I C module operates in master mode by default. To enable slave operation, i.e., to allow the device to be addressed as an I
slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the I
missions as a master, and being addressed as a slave. When operating in the slave mode, HFPERCLK frequency must be higher than
2 MHz for Standard-mode, 5 MHz for Fast-mode, and 14 MHz for Fast-mode Plus.
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495.
Table 17.5. I2C STATE Values
Description
No transmission is being performed by this module.
Waiting for idle. Will send a start condition as soon as the bus is idle.
Start being transmitted
Address being transmitted or has been received
Address ACK/NACK being transmitted or received
Data being transmitted or received
Data ACK/NACK being transmitted or received
Table 17.6. I2C Transmission Status
Description
Set whenever there is activity on the bus. Whether or not this module is responsible for
the activity cannot be determined by this byte.
Set when operating as a master. Cleared at all other times.
Set when operating as a transmitter; either a master transmitter or a slave transmitter.
Cleared at all other times
Set when the bus is held by this I
Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case it is set
if a NACK was received. In all other cases, the bit is cleared.
2
C module, and therefore only held constant as long as the bus is held, i.e., as long as
2
C module and the I
2
C module is at in any ongoing transmission, and a set of single-bits,
Table 17.5 I2C STATE Values on page
2
C module because an action is required by software.
2
C module operates in a mixed mode, both capable of starting trans-
Reference Manual
I2C - Inter-Integrated Circuit Interface
2
C bus are in at a given time. The register
2
C module waiting for a soft-
495. When this field is cleared, the
Table 17.6 I2C
2
C
Rev. 1.1 | 495