Dma Support; Interrupts; Wake-Up - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

17.3.12.7 Clock Low Error
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The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications
are identical. A case may arise when (before an arbitration has been decided upon) the I
START or a STOP condition while the other device is still sending data. In the I
an undefined condition. The I
START or a STOP condition and another device (another master or a misbehaving slave) pulls SCL low before the I
START/STOP condition on SDA, a clock low error is generated. The CLERR interrupt flag is then set in the I2Cn_IF register, any held
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lines are released and the I C device goes to idle.

17.3.13 DMA Support

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The I C module has full DMA support. A request for the DMA controller to write to the I
buffer has room for more data). The DMA controller can write to the transmit buffer using the I2Cn_TXDATA or the I2Cn_TXDOUBLE
register. In order to write to the I2Cn_TXDOUBLE register (i.e., transferring 2 bytes simultaneously to the transmit buffer using the
DMA), DMA_USEBURSTS needs to be set to 1 for the selected DMA channel. This ensures that the transfer is made to the transmit
buffer only when both buffer elements are empty. For performing a DMA write to the I2Cn_TXDATA register, DMA_USEBURSTC needs
to be set to 1 for the selected DMA channel. This ensures that a DMA transfer is made even when the transmit buffer is half-empty.
A request for the DMA controller to read from the I
receive from I2Cn_RXDOUBLE (i.e., receive only when both buffer elements are full), DMA_USEBURSTS needs to be set to 1 for the
selected DMA channel. In order to receive from I2Cn_RXDATA through the DMA, DMA_USEBURSTC needs to be set to 1. This en-
sures that the data gets picked up even when the receive buffer is half-full.

17.3.14 Interrupts

The interrupts generated by the I
will be made if one or more of the interrupt flags in I2Cn_IF and their corresponding bits in I2Cn_IEN are set.

17.3.15 Wake-up

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The I C receive section can be active all the way down to energy mode EM3 Stop, and can wake up the CPU on address interrupt. All
address match modes are supported.
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C deals with this by generating a clock low error. This means that if the I
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C receive buffer can come from RXDATAV (data available in the receive buffer). To
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C module are combined into one interrupt vector, I2C_INT. If I
I2C - Inter-Integrated Circuit Interface
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C module decides to send out a repeated
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C protocol specifications, such a combination results in
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C is transmitting a repeated
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C transmit buffer can come from TXBL (transmit
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C interrupts are enabled, an interrupt
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C sends out the
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