Adcn_Singlectrlx - Single Channel Control Register Continued - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.5.5 ADCn_SINGLECTRLX - Single Channel Control Register Continued

Offset
0x014
Reset
Access
Name
Bit Name
31:29 REPDELAY
Delay value between two repeated conversions.
Value
0
1
2
3
4
5
6
7
28 Reserved
27 CONVSTARTDELAY-
EN
Delay value for next conversion start event.
Value
0
1
26:22 CONVSTARTDELAY
Delay value for next conversion start event in 1us ticks (based on TIMEBASE).
Value
DELAY
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Reset Access Description
0x0 RW REPDELAY Select for SINGLE REP Mode
Mode Description
NODELAY No delay
4CYCLES 4 conversion clock cycles
8CYCLES 8 conversion clock cycles
16CYCLES 16 conversion clock cycles
32CYCLES 32 conversion clock cycles
64CYCLES 64 conversion clock cycles
128CYCLES 128 conversion clock cycles
256CYCLES 256 conversion clock cycles
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Enable Delaying Next Conversion Start
Description
CONVSTARTDELAY is disabled.
CONVSTARTDELAY is enabled.
0x00 RW Delay Value for Next Conversion Start If CONVSTARTDELAYEN is
Set
Description
Delay the next conver-
sion start by (CON-
VSTARTDELAY+1) us
Bit Position
Reference Manual
ADC - Analog to Digital Converter
1.2 Conven-
Rev. 1.1 | 883