14.5.8 WDOG_IEN - Interrupt Enable Register
Offset
0x028
Reset
Access
Name
Bit
Name
31:5
Reserved
4
PEM1
Enable/disable the PEM1 interrupt
3
PEM0
Enable/disable the PEM0 interrupt
2
WIN
Enable/disable the WIN interrupt
1
WARN
Enable/disable the WARN interrupt
0
TOUT
Enable/disable the TOUT interrupt
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Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0
RW
PEM1 Interrupt Enable
0
RW
PEM0 Interrupt Enable
0
RW
WIN Interrupt Enable
0
RW
WARN Interrupt Enable
0
RW
TOUT Interrupt Enable
Bit Position
Reference Manual
WDOG - Watchdog Timer
1.2 Conven-
Rev. 1.1 | 419
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