18.5.27 USARTn_TIMECMP1 - Used to Generate Interrupts and Various Delays
Offset
0x06C
Reset
Access
Name
Bit
Name
31:25
Reserved
24
RESTARTEN
Each TCMP1 event will reset and restart the timer
Value
0
1
23
Reserved
22:20
TSTOP
Select the source which disables comparator 1
Value
0
1
2
3
19
Reserved
18:16
TSTART
Source used to start comparator 1 and timer
Value
0
1
2
3
4
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset
Access
Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0
RW
Restart Timer on TCMP1
Description
Disable the timer restarting on TCMP1
Enable the timer restarting on TCMP1
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
RW
Source Used to Disable Comparator 1
Mode
Description
TCMP1
Comparator 1 is disabled when the counter equals TCMPVAL and trig-
gers a TCMP1 event
TXST
Comparator 1 is disabled at TX start TX Engine
RXACT
Comparator 1 is disabled on RX going going Active (default: low)
RXACTN
Comparator 1 is disabled on RX going Inactive
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0
RW
Timer Start Source
Mode
Description
DISABLE
Comparator 1 is disabled
TXEOF
Comparator 1 and timer are started at TX end of frame
TXC
Comparator 1 and timer are started at TX Complete
RXACT
Comparator 1 and timer are started at RX going going Active (default:
low)
RXEOF
Comparator 1 and timer are started at RX end of frame
Bit Position
Reference Manual
1.2 Conven-
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 601
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