Wdog_Cmd - Command Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

Bit Name
0 EN
Set to enabled watchdog timer.

14.5.2 WDOG_CMD - Command Register (Async Reg)

For more information about asynchronous registers see
Offset
0x004
Reset
Access
Name
Bit Name
31:1 Reserved
0 CLEAR
Clear watchdog timer. The bit must be written 4 watchdog cycles before the timeout.
Value
0
1
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Reset Access Description
0 RW Watchdog Timer Enable
4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 W1 Watchdog Timer Clear
Mode Description
UNCHANGED Watchdog timer is unchanged.
CLEARED Watchdog timer is cleared to 0.
Bit Position
Reference Manual
WDOG - Watchdog Timer
Registers).
1.2 Conven-
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