Bit
Name
14
CNTDIR
The direction of the counter must be set in the OVSSINGLE and EXTCLKSINGLE modes. This bit is ignored in EX-
TCLKQUAD mode as the direction is automatically detected.
Value
0
1
13:12
AUXCNTEV
Selects whether the auxiliary counter responds to up-count events, down-count events or both
Value
0
1
2
3
11:10
CNTEV
Selects whether the regular counter responds to up-count events, down-count events or both
Value
0
1
2
3
9
S1CDIR
S1 gives the direction of counting when in the OVSSINGLE or EXTCLKSINGLE modes. When S1 is high, the count direc-
tion is given by CNTDIR, and when S1 is low, the count direction is the opposite
8
HYST
When hysteresis is enabled, the PCNT will always overflow and underflow to TOP/2.
7
DEBUGHALT
Set to halt the PCNT in debug mode only in OVSSINGLE and OVSQUAD modes. When in EXTCLKSINGLE or EX-
TCLKQUAD modes, DEBUGHALT does not halt the Pulse Counter.
Value
0
1
6
AUXCNTRSTEN
The auxiliary counter, AUXCNT, is asynchronously held in reset when this bit is set. The reset is synchronously released
two PCNT clock edges after this bit is cleared. If an external clock is used, the reset should be performed by setting and
clearing the bit without pending for SYNCBUSY bit.
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Reset
Access
Description
0
RW
Non-Quadrature Mode Counter Direction Control
Mode
Description
UP
Up counter mode.
DOWN
Down counter mode.
0x0
RW
Controls When the Auxiliary Counter Counts
Mode
Description
NONE
Never counts.
UP
Counts up on up-count events.
DOWN
Counts up on down-count events.
BOTH
Counts up on both up-count and down-count events.
0x0
RW
Controls When the Counter Counts
Mode
Description
BOTH
Counts up on up-count and down on down-count events.
UP
Only counts up on up-count events.
DOWN
Only counts down on down-count events.
NONE
Never counts.
0
RW
Count Direction Determined By S1
0
RW
Enable Hysteresis
0
RW
Debug Mode Halt Enable
Description
PCNT is running in debug mode.
PCNT is frozen in debug mode.
0
RW
Enable AUXCNT Reset
Reference Manual
PCNT - Pulse Counter
Rev. 1.1 | 464
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