Usartn_Routepen - I/O Routing Pin Enable Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

18.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register

Offset
0x074
Reset
Access
Name
Bit Name
31:6 Reserved
5 RTSPEN
When set, the RTS pin of the USART is enabled.
Value
0
1
4 CTSPEN
When set, the CTS pin of the USART is enabled.
Value
0
1
3 CLKPEN
When set, the CLK pin of the USART is enabled.
Value
0
1
2 CSPEN
When set, the CS pin of the USART is enabled.
Value
0
1
1 TXPEN
When set, the TX/MOSI pin of the USART is enabled
Value
0
1
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USART - Universal Synchronous Asynchronous Receiver/Transmitter
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW RTS Pin Enable
Description
The USn_RTS pin is disabled
The USn_RTS pin is enabled
0 RW CTS Pin Enable
Description
The USn_CTS pin is disabled
The USn_CTS pin is enabled
0 RW CLK Pin Enable
Description
The USn_CLK pin is disabled
The USn_CLK pin is enabled
0 RW CS Pin Enable
Description
The USn_CS pin is disabled
The USn_CS pin is enabled
0 RW TX Pin Enable
Description
The U(S)n_TX (MOSI) pin is disabled
The U(S)n_TX (MOSI) pin is enabled
Bit Position
Reference Manual
1.2 Conven-
Rev. 1.1 | 605