Cmu_Lfrcoctrl - Lfrco Control Register - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.5.4 CMU_LFRCOCTRL - LFRCO Control Register

Offset
0x020
Reset
Access
Name
Bit Name
31:28 GMCCURTUNE
Set to tune GMC current. This field is updated with the production calibrated value during reset, and the reset value might
therefore vary between devices.
27:26 Reserved
25:24 TIMEOUT
Configures the start-up delay for LFRCO. Do not change while LFRCO is enabled. When starting up the LFRCO after it has
been completely turned off, use TIMEOUT=16cycles. If the LFRCO has been retained on in EM4, then the TIMEOUT=2cy-
cles configuration is also allowed when re-enabling the LFRCO after EM4 exit (as it is still running).
Value
0
1
2
23:22 Reserved
21:20 VREFUPDATE
Specify Vref update rate. This field can be updated with the production test value during reset, and the reset value might
therefore differ.
Value
0
1
2
3
19 Reserved
18 ENDEM
Set to enable dynamic element matching. This improves average frequency accuracy at the cost of increased jitter.
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Reset Access Description
0x8 RW Tuning of Gmc Current
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1 RW LFRCO Timeout
Mode Description
2CYCLES Timeout period of 2 cycles
16CYCLES Timeout period of 16 cycles
32CYCLES Timeout period of 32 cycles
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1 RW Control Vref Update Rate
Mode Description
32CYCLES 32 clocks.
64CYCLES 64 clocks.
128CYCLES 128 clocks.
256CYCLES 256 clocks.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
1 RW Enable Dynamic Element Matching
Bit Position
Reference Manual
CMU - Clock Management Unit
1.2 Conven-
1.2 Conven-
1.2 Conven-
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