Smu_Ppupatd0 - Ppu Privilege Access Type Descriptor 0 - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

12.5.6 SMU_PPUPATD0 - PPU Privilege Access Type Descriptor 0

Set peripheral bits to 1 to mark as privileged access only
Offset
0x050
Reset
Access
Name
Bit Name
31 SMU
Access control only for SMU
30 RTCC
Access control only for RTCC
29 RMU
Access control only for RMU
28:25 Reserved
24 PCNT0
Access control only for PCNT0
23 Reserved
22 LEUART0
Access control only for LEUART0
21 LETIMER0
Access control only for LETIMER0
20 LESENSE
Access control only for LESENSE
19 LDMA
Access control only for LDMA
18 MSC
Access control only for MSC
17 IDAC0
Access control only for IDAC0
16 I2C0
Access control only for I2C0
15 GPIO
Access control only for GPIO
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Reset Access Description
0 RW Security Management Unit access control bit
0 RW Real-Time Counter and Calendar access control bit
0 RW Reset Management Unit access control bit
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Pulse Counter 0 access control bit
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0 RW Low Energy UART 0 access control bit
0 RW Low Energy Timer 0 access control bit
0 RW Low Energy Sensor Interface access control bit
0 RW Linked Direct Memory Access Controller access control bit
0 RW Memory System Controller access control bit
0 RW Current Digital to Analog Converter 0 access control bit
0 RW I2C 0 access control bit
0 RW General purpose Input/Output access control bit
Bit Position
Reference Manual
SMU - Security Management Unit
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 371