Register Map - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

20.4 Register Map

The offset register address is relative to the registers base address.
Offset Name
0x000 TIMERn_CTRL
0x004 TIMERn_CMD
0x008 TIMERn_STATUS
0x00C TIMERn_IF
0x010 TIMERn_IFS
0x014 TIMERn_IFC
0x018 TIMERn_IEN
0x01C TIMERn_TOP
0x020 TIMERn_TOPB
0x024 TIMERn_CNT
0x02C TIMERn_LOCK
0x030 TIMERn_ROUTEPEN
0x034 TIMERn_ROUTELOC0
0x03C TIMERn_ROUTELOC2
0x060 TIMERn_CC0_CTRL
0x064 TIMERn_CC0_CCV
0x068 TIMERn_CC0_CCVP
0x06C TIMERn_CC0_CCVB
... TIMERn_CCx_CTRL
... TIMERn_CCx_CCV
... TIMERn_CCx_CCVP
... TIMERn_CCx_CCVB
0x090 TIMERn_CC3_CTRL
0x094 TIMERn_CC3_CCV
0x098 TIMERn_CC3_CCVP
0x09C TIMERn_CC3_CCVB
0x0A0 TIMERn_DTCTRL
0x0A4 TIMERn_DTTIME
0x0A8 TIMERn_DTFC
0x0AC TIMERn_DTOGEN
0x0B0 TIMERn_DTFAULT
0x0B4 TIMERn_DTFAULTC
0x0B8 TIMERn_DTLOCK
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Type Description
RW Control Register
W1 Command Register
R Status Register
R Interrupt Flag Register
W1 Interrupt Flag Set Register
(R)W1 Interrupt Flag Clear Register
RW Interrupt Enable Register
RWH Counter Top Value Register
RW Counter Top Value Buffer Register
RWH Counter Value Register
RWH TIMER Configuration Lock Register
RW I/O Routing Pin Enable Register
RW I/O Routing Location Register
RW I/O Routing Location Register
RW CC Channel Control Register
RWH(a) CC Channel Value Register
R CC Channel Value Peek Register
RWH CC Channel Buffer Register
RW CC Channel Control Register
RWH(a) CC Channel Value Register
R CC Channel Value Peek Register
RWH CC Channel Buffer Register
RW CC Channel Control Register
RWH(a) CC Channel Value Register
R CC Channel Value Peek Register
RWH CC Channel Buffer Register
RW DTI Control Register
RW DTI Time Control Register
RW DTI Fault Configuration Register
RW DTI Output Generation Enable Register
R DTI Fault Register
W1 DTI Fault Clear Register
RWH DTI Configuration Lock Register
Reference Manual
TIMER/WTIMER - Timer/Counter
Rev. 1.1 | 674