Lesense_Decctrl - Decoder Control Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

28.5.4 LESENSE_DECCTRL - Decoder Control Register (Async Reg)

For more information about asynchronous registers see
Offset
0x00C
Reset
Access
Name
Bit Name
31:29 Reserved
28:25 PRSSEL3
Select PRS input for bit 3 of the LESENSE decoder
Value
0
1
2
3
4
5
6
7
8
9
10
11
24 Reserved
23:20 PRSSEL2
Select PRS input for bit 2 of the LESENSE decoder
Value
0
1
2
3
4
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4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW LESENSE Decoder PRS Input 3 Configuration
Mode Description
PRSCH0 PRS Channel 0 selected as input
PRSCH1 PRS Channel 1 selected as input
PRSCH2 PRS Channel 2 selected as input
PRSCH3 PRS Channel 3 selected as input
PRSCH4 PRS Channel 4 selected as input
PRSCH5 PRS Channel 5 selected as input
PRSCH6 PRS Channel 6 selected as input
PRSCH7 PRS Channel 7 selected as input
PRSCH8 PRS Channel 8 selected as input
PRSCH9 PRS Channel 9 selected as input
PRSCH10 PRS Channel 10 selected as input
PRSCH11 PRS Channel 11 selected as input
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW LESENSE Decoder PRS Input 2 Configuration
Mode Description
PRSCH0 PRS Channel 0 selected as input
PRSCH1 PRS Channel 1 selected as input
PRSCH2 PRS Channel 2 selected as input
PRSCH3 PRS Channel 3 selected as input
PRSCH4 PRS Channel 4 selected as input
LESENSE - Low Energy Sensor Interface
Bit Position
Reference Manual
Registers).
1.2 Conven-
1.2 Conven-
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