Register Description; Wdog_Ctrl - Control Register (Async Reg) - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

14.5 Register Description

14.5.1 WDOG_CTRL - Control Register (Async Reg)

For more information about asynchronous registers see
Offset
0x000
Reset
Access
Name
Bit Name
31 WDOGRSTDIS
Disable watchdog reset output.
Value
0
1
30 CLRSRC
Select watchdog clear source.
Value
0
1
29:27 Reserved
26:24 WINSEL
Select watchdog illegal limit.
Value
0
1
2
3
4
5
6
7
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4.3 Access to Low Energy Peripherals (Asynchronous
Reset Access Description
0 RW Watchdog Reset Disable
Mode Description
EN A timeout will cause a watchdog reset
DIS A timeout will not cause a watchdog reset
0 RW Watchdog Clear Source
Mode Description
SW A write to the clear bit will clear the watchdog counter
PCH0 A rising edge on the PRS Channel0 will clear the watchdog counter
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x0 RW Watchdog Illegal Window Select
Description
Disabled.
Window limit is 12.5% of the Timeout.
Window limit is 25.0% of the Timeout.
Window limit is 37.5% of the Timeout.
Window limit is 50.0% of the Timeout.
Window limit is 62.5% of the Timeout.
Window limit is 75.0% of the Timeout.
Window limit is 87.5% of the Timeout.
Bit Position
Reference Manual
WDOG - Watchdog Timer
Registers).
1.2 Conven-
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