Async Adc_Clk Usage Restrictions And Benefits - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

26.3.15 ASYNC ADC_CLK Usage Restrictions and Benefits

When the ADC_CLK is chosen to come from ASYNCCLK, (ADCCLKMODE is set to ASYNC), the ADC_CLK and the ADC peripheral
clock are considered asynchronous and this adds some restrictions:
• Due to a synchronization delay, accessing the following registers takes extra time (up to additional 7 HFPERCLK cycles):
ADCn_SINGLEDATA, ADCn_SCANDATA, ADCn_SINGLEDATAP, ADCn_SCANDATAP, ADCn_SCANDATAX, ADCn_SCANDA-
TAXP, ADCn_SINGLEFIFOCOUNT, ADCn_SCANFIFOCOUNT, ADCn_SINGLEFIFOCLEAR, ADCn_SCANFIFOCLEAR.
• The safe time to change the ADCn_SINGLECTRL, ADCn_SINGLECTRLX, ADCn_SCANCTRL, ADCn_SCANCTRLx, ADCn_SCA-
NINPUTSEL, ADCn_SCANNEGSEL or ADCn_SCANMASK register is when SINGLEACT/SCANACT in the ADCn_STATUS is 0
with no pending trigger event. The user can enforce this by writing the SINGLESTOP or SCANSTOP in the ADCn_CMD register and
ensuring no trigger event can come before modifying the registers.
• When the ADC needs to run in EM2 Deep Sleep or EM3 Stop, only AUXHFRCO can provide the ADC_CLK to the ADC. Thus the
user needs to set ASYNC mode of ADCCLKMODE and setup the CMU to provide the AUXHFRCO clock as ASYNCCLK.
• If the ADC needs to run on a particular adc_clk_sar frequency to achieve a sample rate and the HFPERCLK is not a proper multiple
for such clock frequency, a higher frequency system clock, HFRCO, can be chosen to be ADC_CLK using ASYNC mode. This al-
lows HFPERCLK to be set to an optimum value from a system view point.
• ASYNC mode can also help with digital noise mitigation as this clock is asynchronous (not balanced) with the system clock. More-
over, the user can use the invert option to invert the source of ASYNCCLK helping in noise mitigation further.
• Whenever ADC is being used in asynchronous mode, then HFPERCLK must be at least 1.5 times higher than the ADC_CLK.
• With ASNEEDED setting for ASYNCCLK request, the ADC_CLK power can be reduced.
26.3.16 Window Compare Function
The ADC supports a window compare function on both the latest single and scan outputs. The compare thresholds, ADGT and ADLT,
are defined in the ADCn_CMPTHR register. These are 16-bit values and their format must match the type of conversion (single-ended
or differential) the user is trying to compare with. For example, a 12-bit differential conversion is sign extended to 16 bits while a 12-bit
single-ended conversion result would get zero padded to 16-bit result before comparing with ADGT and ADLT. If over-sampling is ena-
bled, the conversion result could grow to 16-bits. There is a single set of ADLT and ADGT threshold for both single and scan compare.
The user can however enable single or scan compare logic individually by enabling CMPEN in ADCn_SINGLECTRL or
ADCn_SCANCTRL register.
The user can perform comparison both within or outside of the window defined by the ADGT and ADLT. If the ADLT is greater than
ADGT, the ADC compares if the current sample is within the window. Otherwise, the ADC compares if the current sample is outside of
the window.
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Reference Manual
ADC - Analog to Digital Converter
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