Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual page 873

Bit Name
Value
0
1
2
3
4
5
6
7
8
9
10
11
23 Reserved
22:16 TIMEBASE
Sets the time base used for the ADC warm up sequence based on ADC_CLK. The TIMEBASE field should be set equal to
produce timing of 1us or greater.
Value
TIMEBASE
15 Reserved
14:8 PRESC
Sets the prescale factor to generate the ADC conversion clock (adc_sar_clk) from ADC_CLK.
Value
PRESC
7 ADCCLKMODE
Selects ADC_CLK source as synchronous or asynchronous - with respect to the Peripheral Clock (HFPERCLK).
Value
0
1
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Reset Access Description
Mode Description
X2 2 samples for each conversion result
X4 4 samples for each conversion result
X8 8 samples for each conversion result
X16 16 samples for each conversion result
X32 32 samples for each conversion result
X64 64 samples for each conversion result
X128 128 samples for each conversion result
X256 256 samples for each conversion result
X512 512 samples for each conversion result
X1024 1024 samples for each conversion result
X2048 2048 samples for each conversion result
X4096 4096 samples for each conversion result
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x1F RW 1us Time Base
Description
ADC STANDBY/SLOWACC mode warm-up is set to 1 x (TIMEBASE
+ 1) ADC_CLK cycles and NORMAL mode warm-up is set to 5 x
(TIMEBASE + 1) ADC_CLK cycles.
To ensure compatibility with future devices, always write bits to 0. More information in
tions
0x00 RW Prescalar Setting for ADC Sample and Conversion Clock
Description
Clock prescale factor. ADC_CLK is divided by (PRESC+1) to produce
adc_clk_sar.
0 RW ADC Clock Mode
Mode Description
SYNC Synchronous clocking. Uses HFPERCLK to generate ADC_CLK, ADC
will not be available in EM2 in this mode.
ASYNC Asynchronous clocking. Uses clk_adc_async coming from CMU to
generate ADC_CLK. ADC might be available in EM2 in this mode if the
CLK_ADC_ASYNC is available in EM2
Reference Manual
ADC - Analog to Digital Converter
1.2 Conven-
1.2 Conven-
Rev. 1.1 | 873