Configuration For Operating Frequencies - Silicon Laboratories EFR32xG14 Wireless Gecko Reference Manual

11.3.3 Configuration for Operating Frequencies

The HFXO is capable of frequencies up to 40 MHz, which allows the EFR32 to run at up to this frequency. However the Memory Sys-
tem Controller (MSC) and the Low Energy Peripheral Interface need to be configured correctly to allow operation at higher frequencies
as explained below.
The MODE bitfield in MSC_READCTRL makes sure the flash is able to operate at the given HFCLK frequency by inserting wait states
for flash accesses. The required settings for controlling flash wait states are shown in
quencies, at 1.2V: Flash Wait States on page
eral Interface is able to operate at the given HFBUSCLK
settings are shown in Table 11.4 LE Configuration for Operating Frequencies: Low Energy Peripheral Interface on page
Before going to a high frequency, make sure the registers in the table have the correct values. When going down in frequency, make
sure to keep the registers at the values required by the higher frequency until after the switch has been done.
Table 11.2. MSC Configuration for Operating Frequencies, at 1.2V: Flash Wait States
Condition
HFCLK <= 25 MHz
25 MHz < HFCLK <= 40 MHz
Table 11.3. MSC Configuration for Operating Frequencies, at 1.0V: Flash Wait States
Condition
HFCLK <= 7 MHz
7 MHz < HFCLK <= 14 MHz
Table 11.4. LE Configuration for Operating Frequencies: Low Energy Peripheral Interface
Condition
HFBUSCLK <= 32 MHz
LE
HFBUSCLK > 32 MHz
LE
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302. The WSHFLE bitfield in CMU_CTRL is used to ensure that the Low Energy Periph-
frequency by inserting wait states when using this interface. The required
LE
MODE in MSC_READCTRL
WS0 or above
WS1 or above
MODE in MSC_READCTRL
WS0 or above
WS1 or above
WSHFLE in CMU_CTRL
0 / 1
1
CMU - Clock Management Unit
Table 11.2 MSC Configuration for Operating Fre-
Reference Manual
302.
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